Gilbert, Arizona
United States
63
2026-04-30
The entities that hold a legal rights for patent applications filed by inventor Huemoeller Ronald Patrick:
Ronald Patrick Huemoeller from Gilbert, US has applied for patents for these inventions. The list has both pending applications and granted patents:
SEMICONDUCTOR DEVICE WITH TIERED PILLAR AND MANUFACTURING METHOD THEREOF
#2 | 2026-01-08Method for Collective Dishing of Singulated Dies
#3 | 2025-05-15SEMICONDUCTOR PACKAGE WITH HIGH ROUTING DENSITY PATCH
#4 | 2025-01-30SEMICONDUCTOR DEVICE PACKAGE AND MANUFACTURING METHOD THEREOF
#5 | 2024-08-08SEMICONDUCTOR PACKAGE WITH HIGH ROUTING DENSITY PATCH
#6 | 2024-05-23Method for collective dishing of singulated dies
#7 | 2024-01-18HYBRID BONDING OF SEMICONDUCTOR STRUCTURES TO ADVANCED SUBSTRATE PANELS
#8 | 2023-02-09Semiconductor device package and manufacturing method thereof
#9 | 2022-07-14Semiconductor package with routing patch and conductive interconnection structures laterally displaced from routing patch
#10 | 2021-11-18Encapsulated semiconductor package
#11 | 2021-09-23Semiconductor device with tiered pillar and manufacturing method thereof
#12 | 2020-12-31Semiconductor package with high routing density patch
#13 | 2020-11-19Packaging for fingerprint sensors and methods of manufacture
#14 | 2020-10-29Semiconductor device package and manufacturing method thereof
#15 | 2020-09-17Semiconductor device with tiered pillar and manufacturing method thereof
#16 | 2020-02-27Methods of manufacturing an encapsulated semiconductor device
#17 | 2019-10-29Encapsulated semiconductor package
#18 | 2019-10-24Semiconductor device package and manufacturing method thereof
#19 | 2019-09-19Encapsulated semiconductor package
#20 | 2019-08-01Semiconductor device with tiered pillar and manufacturing method thereof
#21 | 2019-05-07Semiconductor device package and manufacturing method thereof
#22 | 2019-02-07Semiconductor package with high routing density patch
#23 | 2018-11-20Stress relieving through-silicon vias
#24 | 2018-11-13Trace stacking structure and method
#25 | 2018-09-27Semiconductor device with tiered pillar and manufacturing method thereof
#26 | 2018-07-03Embedded component package and fabrication method
#27 | 2018-05-08Semiconductor device package and manufacturing method thereof
#28 | 2018-03-29Packaging for fingerprint sensors and methods of manufacture
#29 | 2017-11-07Encapsulated semiconductor package
#30 | 2017-09-28EMBEDDED DIE IN PANEL METHOD AND STRUCTURE
#31 | 2017-06-29Semiconductor device package and manufacturing method thereof
#32 | 2017-03-28Stress relieving through-silicon vias
#33 | 2017-02-21Embedded die in panel method and structure
#34 | 2017-01-24Semiconductor device package and manufacturing method thereof
#35 | 2016-11-24Packaging for fingerprint sensors and methods of manufacture
#36 | 2016-10-20Semiconductor package with high routing density patch
#37 | 2016-10-04Extended landing pad substrate package structure and method
#38 | 2016-05-24Semiconductor device package and manufacturing method thereof
#39 | 2016-04-26Through via nub reveal method and structure
#40 | 2016-01-05Trace stacking structure and method
#41 | 2015-10-13Through via connected backside embedded circuit features structure and method
#42 | 2015-09-08Embedded component package and fabrication method
#43 | 2015-07-14Through via recessed reveal structure and method
#44 | 2015-06-02Backside warpage control structure and fabrication method
#45 | 2015-05-21Semicondutor device with through-silicon via-less deep wells
#46 | 2015-05-07Interposer, manufacturing method thereof, semiconductor package using the same, and method for fabricating the semiconductor package
#47 | 2015-03-24Method and system for backside dielectric patterning for wafer warpage and stress control
#48 | 2015-01-27Electronic component package fabrication method and structure
#49 | 2014-10-28Extended landing pad substrate package structure and method
#50 | 2014-05-15Method and system for a semiconductor for device package with a die-to-packaging substrate first bond
#51 | 2014-05-15Method and system for a semiconductor device package with a die-to-die first bond
#52 | 2014-05-15Methods for temporary wafer molding for chip-on-wafer assembly
#53 | 2014-05-15Method and system for a semiconductor device package with a die to interposer wafer first bond
#54 | 2014-02-18Electronic component package fabrication method and structure
#55 | 2013-10-08Routable single layer substrate and semiconductor package including same
#56 | 2013-05-14Through via connected backside embedded circuit features structure and method
#57 | 2013-04-30Shielded embedded electronic component substrate fabrication method and structure
#58 | 2013-04-23Bumped chip package
#59 | 2013-03-05Through via recessed reveal structure and method
#60 | 2012-12-04Through via nub reveal method and structure
#61 | 2012-09-11Bumped chip package fabrication method and structure
#62 | 2011-08-09Bumped chip package fabrication method and structure
#63 | 2010-11-30Ultra thin package and fabrication method
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