Memory circuits and methods of making and designing the same

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of U.S. Provisional Application Ser. No. 61/576,254, filed on Dec. 15, 2011, the contents of which are incorporated by reference herein, in their entirety.

TECHNICAL FIELD

The present invention relates generally to memory circuits and methods, and more particularly to latch based memory circuits with high body effect transistors, and methods of designing memory cells.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a side cross sectional view showing a deeply depleted channel (DDC) transistor that can be included in embodiments.

FIG. 1B is a side cross sectional view showing various transistor types that can be included in embodiments.

FIG. 1C is a flow diagram showing methods of fabricating DDC transistors according to embodiments.

FIGS. 2A-0 and 2A-1 are diagrams of a storage circuit and transistors therefor, according to embodiments.

FIG. 2B is a block schematic diagram of a static random access memory (SRAM) device according to an embodiment.

FIG. 3A is a block schematic diagram of a SRAM device according to another embodiment.

FIG. 3B is a block schematic diagram of a SRAM device according to a further embodiment.

FIG. 3C shows read and write failure rates for an SRAM cell at different stages of a design process to reduce VDDmin.

FIG. 4A is a flow diagram of a method according an embodiment.

FIG. 4B is a diagram showing threshold variations candidates that can be evaluated in a method like that of FIG. 4A.

FIG. 5A is an isoplot of bit failure rates for an SRAM device according to one embodiment.

FIG. 5B is an isoplot of bit failure rates for the SRAM device of FIG. 5A at a lower power supply voltage, according to one embodiment.

DETAILED DESCRIPTION

Various embodiments of the present invention will now be described in detail with reference to a number of drawings. The embodiments show circuits and methods related to an integrated circuit device having transistors that have an enhanced body coefficient. The embodiments described herein also show circuits and methods related to an integrated circuit having improved transistor matching, such that the transistors have reduced variability of threshold voltage and body coefficient. Particular embodiments may include latch type memory elements, such as static random access memories (SRAMs) having enhanced cell stability and capable of operation at reduced power supply voltages, as compared to SRAMs employing conventional transistors.

FIG. 1A shows an embodiment of a deeply depleted channel (DDC) transistor 100 that is configured to have an enhanced body coefficient, along with the ability to set a threshold voltage (Vt) with enhanced precision, according to certain described embodiments. The DDC transistor 100 includes a gate electrode 102, source 104, drain 106, and a gate dielectric 128 positioned over a substantially undoped channel 110. In the embodiment shown, lightly doped source and drain extensions (SDE) 132, positioned respectively adjacent to source 104 and drain 106, extend toward each other, reducing effective length of the substantially undoped channel 110. In alternate embodiments, a DDC transistor may not include SDEs 132.

In FIG. 1A, the DDC transistor 100 is shown as an N-channel transistor having a source 104 and drain 106 made of N-type dopant material, formed upon a substrate such as a P-type doped silicon substrate providing a P-well 114 formed on a substrate 116. In addition, the N-channel DDC transistor in FIG. 1A includes a highly doped screening region 112 made of P-type dopant material, and a threshold voltage set region 111 made of P-type dopant material. However, it will be understood that, with appropriate change to substrate or dopant material, a p-channel DDC transistor can be formed from suitable substrates.

In one embodiment, a process for forming the DDC transistor begins with forming the screening region 112. In certain embodiments, the screening region 112 is formed by implanting dopants into the P-well 114. In alternative embodiments the screening region is formed on the P-well using methods such as in-situ doped epitaxial silicon deposition, or epitaxial silicon deposition followed by dopant implantation. The screening region formation step can be before or after the formation of isolation structures, such as STI (shallow trench isolation) formation, depending on the application and results desired. Boron (B), Indium (I), or other P-type materials may be used for P-type implants, and arsenic (As), antimony (Sb) or phosphorous (P) and other N-type materials can be used for N-type implants. In certain embodiments, the screening region 112 can have a dopant concentration between about 1×10¹⁹ to 5×10²⁰ dopant atoms/cm³, with 5×10¹⁹ being typical, the dopant concentration being selected to achieve the desired characteristics of the transistor such as reductions in drain induced barrier lowering (DIBL), on and off current (Ion vs. Ioff) and so on, with the concentration sufficiently high to effectively pin the depletion width of the channel for a given gate voltage. A carbon (C), or other dopant migration resistant layer can be applied above the screening region to reduce upward migration of dopants, particularly to inhibit the migration of boron dopants. Preferably, the carbon is preceded by a germanium implant to facilitate the traveling of the carbon atoms into lattice sites that inhibit migration of boron. The dopant migration resistant layer can be implanted into the screening region or provided as an in-situ doped epitaxial layer.

In certain embodiments, a threshold voltage set region 111 is positioned above the screening region 112, and is typically formed as a thin doped layer. The threshold voltage set region 111 can be either adjacent to the screening region or vertically offset from the screening region. In certain embodiments, the threshold voltage set region 111 is formed by delta doping, controlled in-situ deposition, or atomic layer deposition. In alternative embodiments, the threshold voltage set region 111 can be formed by way of an in-situ doped epitaxial layer that is grown above the screening region 112, or by epitaxial growth of a layer of silicon followed by diffusion of dopant atoms from the screening region. In certain embodiments, suitably varying dopant concentration, and thickness of the threshold voltage set region 111, as well as separation of the threshold voltage set region 111 from the gate dielectric 128 and the screening region 112 allows for slight adjustments of threshold voltage in the operating transistor. In certain embodiments, the threshold voltage set region 111 can have a dopant concentration between about 1×10¹⁸ dopant atoms/cm³ and about 1×10¹⁹ dopant atoms per cm³. In alternative embodiments, the threshold voltage set region 111 can have a dopant concentration that is approximately less than half of the concentration of dopants in the screening region 112.

In certain embodiments, the formation of the threshold voltage set region 111 is followed by non-selective blanket epitaxial (EPI) deposition step that forms the substantially undoped channel region 110. In alternative embodiments, the non-selective blanket EPI deposition step is performed after forming the screening region 112, and the threshold voltage setting region 111 is formed by controlled outdiffusion of dopants from the screening region 112 into a portion of the blanket EPI layer, as described below. Dopant migration resistant layers using, for instance, C or the like can be applied above and below the threshold voltage set region 111 to prevent dopant migration from the threshold voltage set region 111 into the substantially undoped channel region 110, or alternatively from the screening region 112 into the threshold voltage set region 111, particularly in the case of using boron for the threshold voltage set region. Isolation structures (e.g., STI) can be formed after the non-selective blanket EPI deposition step, and can include the formation of a low temperature trench sacrificial oxide liner, at a temperature lower than 900° C.

In addition to using dopant migration resistant layers, other techniques can be used to reduce upward migration of dopants from the screening region 112 and the threshold voltage set region 111, including but not limited to low temperature processing, selection or substitution of low migration dopants such as antimony or indium, low temperature or flash annealing to reduce interstitial dopant migration, or any other suitable technique to reduce movement of dopant atoms can be used.

The substantially undoped channel region 110 is positioned above the threshold voltage set region 111. In certain embodiments the substantially undoped channel region 110 can have a dopant concentration less than 5×10¹⁷ dopant atoms per cm³ adjacent or near the gate dielectric 128. In alternative embodiments, the substantially undoped channel region 110 can have a dopant concentration that is approximately less than one tenth of the dopant concentration in the screening region 112. In one embodiment, the thickness of the substantially undoped channel region 110 can range from 5 to 50 nanometers (nm), with exact thickness being dependent on desired transistor operating characteristics and transistor design node (i.e., a 20 nm gate length transistor will typically have a thinner channel thickness than a 45 nm gate length transistor).

A gate stack may be formed or otherwise constructed above the substantially undoped channel region 110 in a number of different ways, from different materials, and of different work functions. In one embodiment, the gate stack can be formed using a gate-first process that includes SiON/polysilicon(Poly) or SiON/Metal/Poly. In an alternative embodiment, the gate stack can be formed using a gate-last process that includes a high-k/metal gate stack wherein the gate stack can either be formed with “Hi-k first-Metal gate last” flow or “Hi-k last-Metal gate last” flow. Yet another option, is a metal gate that includes a tunable range of work functions depending on the device construction, N(NMOS)/P(PMOS)/N(PMOS)/P(NMOS)/Mid-gap or Band-edge or anywhere in between. Next, Source/Drain tips (SDEs) may be implanted, or optionally may not be implanted depending on the application. The dimensions of the tips can be varied as required, and will depend in part on dimensions of gate spacers (SPGR) 130. Next, in optional steps, PMOS or NMOS epi layers may be formed in the source and drain regions as performance enhancers for creating strained channels. For gate-last processes a gate-last module is formed.

The source 104 and drain 106 can be formed preferably using conventional dopant ion implantation processes and materials, and may include, for example, modifications such as stress inducing source/drain structures, raised and/or recessed source/drains, asymmetrically doped, counter-doped or crystal structure modified source/drains, or implant doping of source/drain extension regions according to SDE techniques. The channel 110 contacts and extends between the source 104 and the drain 106, and supports movement of mobile charge carriers between the source and the drain.

For some embodiments of the DDC transistor 100, when gate electrode voltage is applied at a predetermined level, a depletion region formed in the substantially undoped channel 110 can substantially extend to the screening region 112, since channel depletion depth is a function of the integrated charge from dopants in the doped channel lattice, and the substantially undoped channel 110 has very few dopants. In certain embodiments, at least part of the depletion region extends from the gate dielectric through the substantially undoped channel 110 and a short distance into the highly doped screening region 112 when the predetermined voltage is applied to the gate.

Overall improvement of noise and electrical characteristics for a transistor require careful trade-offs to be made in doping density, length, and depth of the foregoing transistor structures. Improvements made in one area, for example, channel mobility, can be easily offset by adverse short channel effects or greater variability in capacitance or output resistance. One parameter for analog and digital transistor design is the threshold voltage (Vt) at which the transistor can be determined to switches between on or off.

The threshold voltage of the DDC transistor 100 can be adjusted by controlling the dopant concentration and position of the threshold voltage set region 111, while leaving the bulk of the channel region 110 substantially undoped.

By contrast, the threshold voltage in conventional field effect transistors (FETs) can be set by directly implanting a “threshold voltage implant” into the channel raising the threshold voltage to an acceptable level that reduces transistor off-state leakage while still allowing speedy transistor switching. Alternatively, in a conventional FET the Vt can also be set by a technique variously known as “halo” implants, high angle implants, or pocket implants. Such implants create a localized, graded dopant distribution near a transistor source and drain that extends into the channel. Halo implants are often required by transistor designers who want to reduce unwanted source/drain leakage conduction or “punch through” current, but have the added advantage of adjusting threshold voltage. Unfortunately halo implants introduce additional process steps, thereby increasing the manufacturing cost. The use of halo implants also results in the introduction of additional dopants in unwanted locations in the channel. These additional dopants increase the variability of threshold voltage between transistors, and decrease mobility and channel transconductance due to the adverse effects of dopant scattering centers in the channel. In a typical manufacturing flow, halo implants generally require at least two separate processing steps with the die wafer being rotated between different positions (e.g. 0, 90, 180, or 270 degrees), and die with multiple transistor types can even require multiple separate halo implants.

Since advanced die manufacturing processes currently require dozens of high angle implants, eliminating or greatly reducing the number of halo implants is desirable for reducing manufacture time and simplifying die processing. For transistors having poly gate structures, threshold voltage setting via halo implants also introduces additional variation in the threshold voltage, since at least a portion of the halo implant can travel through the corner of the poly gate.

Since poly gate sidewall shape and crystal structure affect final location of halo dopants in the channel, unavoidable variation in poly gate edge shape and poly gate crystal structure will result in further variations in threshold voltage. Such transistor variation is undesirable as it can reduce performance of circuit, and is of particular concern for paired analog transistors that rely on close matching of transistor characteristics for best performance.

While they may be useful for setting threshold voltage in conventional transistors, both halo implants and threshold voltage implant into a previously undoped channel result in permanent contamination of the channel, along with a consequent decrease in channel carrier mobility and increase in transistor threshold voltage variation (due to unavoidable variations in channel dopant density).

By contrast, the techniques for forming the DDC transistor 100 use different threshold voltage modification techniques that do not rely on halo implants (i.e., haloless processing) to set the threshold voltage to a desired range. The techniques for forming the DDC transistor can also maintain a substantially undoped channel near the gate, unlike the conventional process for setting the threshold voltage that involves a shallow implant just below the gate. This advantageously reduces cost of manufacture because halo implant process steps are not required, reduces the chance of failure due to misaligned halo implants, and eliminates unwanted contamination of the undoped channel. Haloless processing can be used alone or in combination, with various other threshold voltage setting structures and techniques, including screening region placement, positioning of intermediate threshold voltage set regions, dopant profiles in the screen and/or threshold voltage set regions, gate metal selection, lightly doped drain geometry adjustments, and application of bias to the screening region. Each of these modified structures and/or haloless processing techniques will be discussed in the following description.

As previously noted, a screening region 112 is a highly doped layer that typically contains dopant atoms with a concentration of between 1×10¹⁸ atoms per cm³ and 1×10²⁰ atoms per cm³, positioned under the channel 110 defined below the gate dielectric 128. P-type dopants such as boron are selected for screening regions of NMOS transistors, while N-type dopants such as arsenic, antimony or phosphorus can be selected for PMOS transistors. The screening region below the substantially undoped channel 110 defines a depletion zone beneath the gate. Generally, the greater the distance screening region 112 is positioned from the gate dielectric 128, the lower the threshold voltage, and conversely, the closer screening region 112 is to the gate dielectric 128, the higher the threshold voltage. In certain embodiments, screening region 112 can contact the source and drain, or optionally, it can be positioned at a greater distance below the gate to avoid direct contact with the source and the drain (not shown). In certain embodiments, it may be formed as a blanket or sheet extending under multiple source/drain/channel regions, while in other embodiments it may be a self-aligned implant or layer coextensive with the substantially undoped channel 110 or a layer extending between outer edges of the gate spacers 130. The screening region thickness can typically range from 5 to 100 nanometers. The screening region 112 is highly doped relative to the substantially undoped channel, the threshold voltage set region (if provided), and the substrate supported well. The peak dopant concentration of the screening region can be ten times or greater than dopant concentration of the substantially undoped channel, with a relative concentration that can be between ten to a hundred times the dopant concentration of the substantially undoped channel 110. In practice, the screening region 112 can be doped to have a near uniform concentration of between 5×10¹⁸ atoms/cm³ and 5×10¹⁹ atoms/cm³. However, embodiments in which the screening region has complex dopant profile or reduces sharply in concentration from an initial spike are also contemplated. In certain embodiments, dopant migration resistant layers of carbon, germanium, or the like can be applied along with or above screening region to prevent dopant migration into the optional threshold voltage set region and the substantially undoped channel.

As will also be appreciated, position, concentration, and thickness of the screening region 112 can affect performance of a DDC transistor. In certain embodiments, peak concentration of the screening region is near the edge of the depletion layer under the gate and the screening region is located above the bottom of the source and drain junctions. Multiple delta doping implants, broad dopant implants, or long duration in-situ substitutional doping is preferred, since the screening region 112 should have a finite thickness, with 10 nm or greater being preferred. When transistors are configured to have such screening regions, the transistor can simultaneously have good threshold voltage matching, high output resistance, low junction leakage, good short channel effects, and still have an independently controlled and strong body effect. In addition, DDC transistors can be used to provide multiple transistors having different threshold voltages on the same die by controlling the position and dopant concentration of the threshold voltage set region 111 and/or the screening region 112, and by controlling the thickness of the substantially undoped channel region 110. Simultaneous provision of these features is difficult for conventional transistors of a similar size. In contrast, DDC transistors designed to have a substantially undoped channel, optional threshold voltage set region (as discussed herein), and a thick and highly doped screening region can simultaneously provide all of the transistor device parameters required for implementation of complex multi-transistor SOC or multi-transistor analog integrated circuits In one embodiment, the screening region is positioned such that the top surface of the screening region is located approximately at a distance of Lg/1.5 to Lg/5 below the gate (where Lg is the gate length). In one embodiment, the threshold voltage set region has a dopant concentration that is approximately 1/10 of the screening region dopant concentration. In certain embodiments, the threshold voltage set region is thin so that the combination of the threshold voltage set region and the screening region is located approximately within a distance of Lg/1.5 to Lg/5 below the gate.

Modifying threshold voltage by use of a threshold voltage set region 111 positioned above the screening region 112 and below the substantially undoped channel 110 is an alternative technique to conventional threshold voltage implants for adjusting threshold voltage. Care must be taken to prevent dopant migration into the substantially undoped channel 110, and use of low temperature anneals and transistor processing is recommended for many applications. The threshold voltage set region thickness can typically range from 2 to 20 nanometers. The threshold voltage set region 111 is highly doped relative to the substantially undoped channel 110, but is typically doped to a level one-half to one-tenth that of the screening region 112. However, embodiments in which the threshold voltage set region has complex dopant profile are also contemplated. Like the screening region, in certain embodiments, dopant migration resistant layers of carbon, germanium, or the like can be applied along with or above the threshold voltage set region to prevent dopant migration into the substantially undoped channel. The threshold voltage set region 111 can be formed by out-diffusion from the screening region 112 into an epitaxially grown layer, by implant or in-situ growth of an epitaxial layer on top of the screening region 112, by delta doping to form an offset doped plane (as disclosed in pending U.S. patent application Ser. No. 12/895,785 filed Sep. 30, 2010, the entirety of which disclosure in herein incorporated by reference), or any other conventional or known doping techniques.

Yet another technique for modifying threshold voltage relies on selection of a gate material having a suitable work function. The gate electrode 102 can be formed from conventional materials, preferably including, but not limited to, metals, metal alloys, metal nitrides and metal silicides, as well as laminates thereof and composites thereof. In certain embodiments the gate electrode 102 may also be formed from polysilicon, including, for example, highly doped polysilicon and polysilicon-germanium alloy. Metals or metal alloys may include those containing aluminum, titanium, tantalum, or nitrides thereof, including titanium containing compounds such as titanium nitride. Formation of the gate electrode 102 can include silicide methods, chemical vapor deposition methods and physical vapor deposition methods, such as, but not limited to, evaporative methods and sputtering methods. Typically, the gate electrode 102 has an overall thickness from about 1 to about 500 nanometers. In certain embodiments, metals having work functions intermediate between band edge and mid-gap can be selected. As discussed in pending U.S. patent application Ser. No. 12/960,266 filed Dec. 3, 2010, the entirety of which disclosure in herein incorporated by reference, such metal gates simplify swapping of PMOS and NMOS gate metals to allow a reduction in mask steps and different required metal types for systems on a chip or other die supporting multiple transistor types.

Threshold voltage can also be modified by adjustments to lightly doped source and drain extensions (SDE) 132, source/drain extensions that are typically formed by out-diffusion under gate spacers. Source/drain extensions slightly reduce channel length (L_G) by extending the source/drain toward each other using dopant implants of the same dopant type as the source and drain. Care must be taken to control dopant migration to keep the channel extending between the source and drain regions substantially undoped, with a dopant concentration of less than 5×10¹⁷ dopant atoms per cm³. As will be appreciated, variations in extension dimensions affect channel electrical characteristics, and also result in adjustments to threshold voltage. As shown in FIG. 1A, the SDE 132 are symmetrically spaced and extending toward each other with a predetermined length that can be optionally increased or decreased to change threshold voltage. In other embodiments, asymmetrical SDE's are possible, with, for example, the SDE proximate to the source 104 being configured to extend a greater or lesser extent into the channel, having a greater or lesser dopant density, or extending deeper downward or shallower, than the SDE proximate to the drain 106.

Applied bias to the screening region 112 is yet another technique for modifying threshold voltage of the DDC transistor 100. The screening region 112 sets the body effect for the transistor and allows for a higher body effect than is found in conventional FET technologies. For example, a body tap 126 to the screening region 112 of the DDC transistor 100 can be formed in order to provide further control of threshold voltage. The applied bias can be either reverse or forward biased, and can result in significant changes to threshold voltage. Bias can be static or dynamic, and can be applied to isolated transistors, or to groups of transistors that share a common well. Biasing can be static to set threshold voltage at a fixed set point, or dynamic, to adjust to changes in transistor operating conditions or requirements. Various suitable biasing techniques are disclosed in U.S. Pat. No. 8,273,617 issued Sep. 25, 2012, the entirety of which disclosure is incorporated herein by reference.

FIG. 1B is an illustration schematically showing four different transistor types constructed on a common substrate 116 to have a common screening region 112 and epitaxially deposited blanket layer on which a channel for a field effect or other transistor is deposited. The four transistor types illustrated in FIG. 1B include a DDC transistor 100, a slightly depleted channel (SDC) transistor 160, a legacy transistor 140, and an analog undoped transistor 150. The threshold voltage set region 111 and the substantially undoped channel region 110 for the DDC transistor 100 are formed in the blanket epitaxial layer, in accordance with the embodiments described herein.

An SDC transistor 160 can have a screening layer doped to have the same or similar dopant concentration as DDC transistor 100. However, it is distinct from the DDC 100 transistor in that implants, in-situ epitaxial growth, screen layer out-diffusion, or other dopant positioning method is used to place a significant amount of dopants in the channel 164 that is formed in the blanket epitaxial layer. The concentration and uniformity of dopants can vary, but will be intermediate between DDC transistors that normally are substantially undoped, and highly doped conventional or legacy transistors as hereafter described. Because of the channel dopants, such devices can be better matched to legacy device types than undoped channel DDC transistors.

Advantageously, such circuits utilizing SDC transistors can reduce redesign requirements, can match channel functionality of legacy circuits more closely, and may not need auxiliary bias, such as body bias. In addition, short channel effects are improved, allowing an increase in the SDE dose that provides higher drive current than comparable DDC transistors. As will be appreciated, while mobility in the channel is improved relative to a legacy transistor, and Vt variations are reduced, an SDC transistor will not generally have mobility and low Vt variations of a comparable device. Embodiments of various SDC transistor structures and manufacturing processes are more completely described in U.S. patent application Ser. No. 13/469,201 filed May 11, 2012, titled Epitaxial Channel Transistors and Die with Diffusion Doped Channels, by Lucian Shifren et al, the entirety of which disclosure is incorporated by reference herein.

A legacy transistor 140 is a conventional FET having dopants in the channel 144 as described above.

An analog undoped transistor 150 can have a channel 154 that is substantially undoped, having no threshold voltage, channel, or halo implants. Such transistors can have extremely low noise operation, and may not even require lightly doped drains (LDDs) or other structures for operation.

FIG. 1C is a flow diagram 172 illustrating a general method for forming a DDC transistor having an enhanced body coefficient and reduced variability in threshold voltage (a Vt), in accordance with various embodiments. The method illustrated in FIG. 1C is intended to be general and broad in its description, and more detailed embodiments and examples are set forth below. Each block in the flow diagram is illustrated and described in further detail below, in conjunction with the various alternatives associated with each block illustrated in FIG. 1C.

In step 174, the process begins at well formation, which can include one or more different process steps in accordance with different embodiments. The well formation step 174 includes the steps for forming the screening region 112, the threshold voltage set region 111 (if present), and the substantially undoped channel 110.

As indicated by 176, the well formation 174 can be before or after the formation of an isolation structure (e.g., STI) 178.

The well formation 174 can include forming the screening region 112 by implanting dopants into the P-well 114, followed by an EPI pre-clean process that is followed by a blanket or selective EPI deposition. Various alternatives for performing these steps are illustrated in FIG. 1C. In accordance with one embodiment, well formation 174 can include a beam line implant of Ge/B (N), As (P), followed by an epitaxial (EPI) pre-clean process, and followed by a non-selective (blanket) EPI deposition, as shown in 174A.

Alternatively, the well formation 174 can include using a plasma implant of B (N), As (P), followed by an EPI pre-clean, then a non-selective (blanket) EPI deposition, as shown in 174B. The well formation 174 can alternatively include a solid-source diffusion of B(N), As(P), followed by an EPI pre-clean, and followed by a non-selective (blanket) EPI deposition, as shown in 174C. As yet another alternative, well formation 174 can also include well implants, followed by in-situ doped selective EPI of B (N), P (P) as shown in 174D. As will be described further below, the well formation can be configured with different types of devices in mind, including DDC transistors, legacy transistors, high V_T transistors, low V_T transistors, improved σV_T transistors, and standard or legacy σV_T transistors. Embodiments described herein allow for any one of a number of devices configured on a common substrate with different well structures and according to different parameters.

In step 174, Boron (B), Indium (I), or other P-type materials can be used for P-type implants, and arsenic (As), antimony (Sb) or phosphorous (P) and other N-type materials can be used for N-type implants. In certain embodiments, the screening region 110 can have a dopant concentration between about 5×10¹⁸ to 1×10²⁰ dopant atoms/cm³, with the selected dopant concentration dependent on the desired threshold voltage as well as other desired transistor characteristics. A germanium (Ge), carbon (C), or other dopant migration resistant layer can be incorporated above the screening region to reduce upward migration of dopants. The dopant migration resistant layer can be formed by way of ion implantation, in-situ doped epitaxial growth or other process. In certain embodiments, a dopant migration resistant layer can also be incorporated to reduce downward migration of dopants.

In certain embodiments of the DDC transistor, a threshold voltage set region 111 is positioned above the screening region 112. The threshold voltage set region 111 can be either adjacent to, incorporated within or vertically offset from the screening region. In certain embodiments, the threshold voltage set region 111 is formed by delta doping, controlled in-situ deposition, or atomic layer deposition. In alternative embodiments, the threshold voltage set region 111 can be formed by way of controlled outdiffusion of dopant material from the screening region 112 into an undoped epitaxial layer, or by way of a separate implantation into the substrate following formation of the screening region 112, before the undoped epitaxial layer is formed. Setting of the threshold voltage for the transistor is implemented by suitably selecting dopant concentration and thickness of the threshold voltage set region 111, as well as maintaining a separation of the threshold voltage set region 111 from the gate dielectric 128, leaving a substantially undoped channel layer directly adjacent to the gate dielectric 128. In certain embodiments, the threshold voltage set region 111 can have a dopant concentration between about 1×10¹⁸ dopant atoms/cm³ and about 1×10¹⁹ dopant atoms per cm³. In alternative embodiments, the threshold voltage set region 111 can have a dopant concentration that is approximately less than half of the concentration of dopants in the screening region 112.

In certain embodiments, an over-layer of the channel is formed above the screening region 112 and threshold voltage set region 111 by way of a blanket or selective EPI deposition (as shown in the alternatives shown in 174A-D), to result in a substantially undoped channel region 110 of a thickness tailored to the technical specifications of the device. As a general matter, the thickness of the substantially undoped channel region 110 ranges from approximately 5-25 nm, with the selected thickness based upon the desired threshold voltage for the transistor. Preferably, a blanket EPI deposition step is performed after forming the screening region 112, and the threshold voltage setting region 111 is formed by controlled outdiffusion of dopants from the screening region 112 into a portion of the blanket EPI layer, as described below. Dopant migration resistant layers of C, Ge, or the like can be utilized as needed to prevent dopant migration from the threshold voltage set region 111 into the substantially undoped channel region 110, or alternatively from the screening region 112 into the threshold voltage set region 111.

In addition to using dopant migration resistant layers, other techniques can be used to reduce upward migration of dopants from the screening region 112 and the threshold voltage set region 111, including but not limited to low temperature processing, selection or substitution of low migration dopants such as antimony or indium, low temperature or flash annealing to reduce interstitial dopant migration, or any other technique to reduce movement of dopant atoms can be used.

As described above, the substantially undoped channel region 110 is positioned above the threshold voltage set region 111. Preferably, the substantially undoped channel region 110 has a dopant concentration less than 5×10¹⁷ dopant atoms per cm³ adjacent or near the gate dielectric 128. In some embodiments, the substantially undoped channel region 110 can have a dopant concentration that is specified to be approximately less than one tenth of the dopant concentration in the screening region 112. In still other embodiments, depending on the transistor characteristics desired, the substantially undoped channel region 110 may contain dopants so that the dopant concentration is elevated to above 5×10¹⁷ dopant atoms per cm³ adjacent or near the gate dielectric 128 or by using a very light dose of halo implants. Preferably, the substantially undoped channel region 110 remains substantially undoped by avoiding the use of high dosage halo or other channel implants.

Referring still to FIG. 1C, STI formation 178, which, again, can occur before or after well formation 174, can include a low temperature trench sacrificial oxide (TSOX) liner, which is formed at a temperature lower than 900° C. as shown by 178A. Embodiments that form the STI structures after the blanket EPI deposition step, using a process that remains within a low thermal budget, can reduce dopant migration from the previously formed screening region 112 and threshold voltage setting region 111.

As shown in step 180, a gate stack can be formed or otherwise constructed above the substantially undoped channel region 110 in a number of different ways, from different materials, and of different work functions. One option is a Poly/SiON gate stack 180A. Another option is a gate-first process 1808 that includes SiON/Metal/Poly and/or SiON/Poly, followed by High-K/Metal Gate. Another option, a gate-last process 180C includes a high-K/metal gate stack wherein the gate stack can either be formed with “Hi-K first-Metal gate last” flow or and “Hi-K last-Metal gate last” flow. Yet another option, 180D is a metal gate that includes a tunable range of work functions depending on the device construction. Preferably, the metal gate materials for n-channel MOS (NMOS) and p-channel MOS (PMOS) are selected to near mid-gap, to take full advantage of the DDC transistor. However, traditional metal gate work function band-gap settings may also be used. In one scheme, metal gate materials can be switched between NMOS and PMOS pairs as a way to attain the desired work functions for given devices.

A gate stack may be formed or otherwise constructed above the substantially undoped channel region 110 in a number of different ways, from different materials including polysilicon and metals to form what is known as “high-k metal gate”. The metal gate process flow may be “gate first” or “gate last”. Preferably, the metal gate materials for NMOS and PMOS are selected to near mid-gap, to take full advantage of the DDC transistor. However, traditional metal gate work function band-gap settings may also be used. In one scheme, metal gate materials can be switched between NMOS and PMOS pairs as a way to attain the desired work functions for given devices. Following formation of the gate stack, source/drain portions may be formed. Typically, the extension portions are implanted, followed by additional spacer formation and then implant or, alternatively, selective epitaxial deposition of deep source/drain regions.

In step 182, Source/Drain tips can be implanted. The dimensions of the tips can be varied as required, and will depend in part on whether gate spacers (SPGR) are used. In one embodiment, Source/Drain tips are not formed (step 182A), and there may be no tip implant.

In step 184, the source 104 and drain 106 can be formed preferably using conventional processes and materials such as ion implantation (184A) and in-situ doped epitaxial deposition (184B). Optionally, as shown in step 184C, PMOS or NMOS selective EPI layers can be formed in the source and drain regions as performance enhancers for strained channels. Source 104 and drain 106 can further include raised and/or recessed source/drains, asymmetrically doped, counter-doped or crystal structure modified source/drains, or implant doping of source/drain extension regions according to LDD (lightly doped drain) techniques, provided that the thermal budget for any anneal steps be within the boundaries of what is required to keep the screening region 112 and threshold voltage setting region 111 substantially intact.

In step 186, a metal gate is formed in accordance with a gate last process. Step 186 is optional and may be performed only for gate-last processes (186A).

Referring to FIG. 2A-0, an integrated circuit device according to an embodiment is shown in a block diagram and designated by the general reference character 200-A. Integrated circuit device 200-A can be a latch type circuit for storing complementary data values on storage nodes SN1/SN2.

Integrated circuit device 200-A can include p-channel transistors 235/240 having sources connected to a first power supply node 291, and gates and drains that cross-coupled between storage nodes (SN1/SN2). That is a gate of transistor 235 can be connected to node SN1, while its drain is connected to node SN2, and a gate of transistor 240 can be connected to node SN2, while its drain is connected to node SN1.

Integrated circuit device 200-A can also include n-channel transistors 245/250 having sources connected to a second supply node VSS, and gates and drains that cross-coupled between storage nodes (SN1/SN2).

A power supply circuit 215 can provide a first power supply voltage VDD to supply node 291, as well as a body bias voltage VBN to bodies of n-channel transistors 245/250. Body bias voltage VBN can be different than a second power supply voltage VSS.

FIG. 2A-1 shows n-channel transistors 245/250 that can be included in the embodiment of FIG. 2A-0. N-channel transistors 245/250 can have a highly doped screening region 212, as described herein or equivalents. Optionally, transistors 245/250 can include any of: a threshold voltage set region 211, SDEs 232, a substantially undoped channel 210/254 (with or without SDEs), or a lightly doped channel 264 (such as that for an SDC transistor as described herein, or equivalents). In very particular embodiments, n-channel transistors 245/250 can match one another, and take the form of any of: DDC transistors, SDC transistors, or analog undoped channel transistors, as described herein, or an equivalent.

P-channel transistors 235/240 can take various forms, including but not limited to DDC transistors, SDC transistors, analog undoped channel transistors, or legacy transistors, as described herein, or an equivalent.

In alternate embodiments, conductivities of the integrated circuit device of FIG. 2A-0 can be switched, with p-channel transistors having a highly doped screening region, and the n-channel transistors having any of various forms, including legacy transistors.

An integrated circuit device 200-A designed with DDC or SDC transistors or both, have enhanced performance characteristics as compared to latches using conventional MOSFETs. Such enhanced performance is a result of, among other things, lower threshold voltage variation, i.e., lower σV_T (for DDC, SDC, and analog undoped channel transistors), higher I_eff and higher body coefficient. This can lead to lower minimum operating voltage (i.e., VDD−VSS) and the ability to design the integrated circuit device 200-A with tighter design corners for improved performance.

Referring initially to FIG. 2B, an integrated circuit device according to another embodiment is shown in a block diagram and designated by the general reference character 200-B. Integrated circuit 200-B is a static random access memory (SRAM) array that may include a number of SRAM cells, including SRAM cells arranged in multiple rows and columns. For ease of discussion, however, only two SRAM cells 205 and 210 are illustrated and discussed along with the associated column power supplies 215 and 220 to generate the applied power supply and other voltages. The SRAM cells embodied at 205 and 210 are implemented using DDC transistors.

In FIG. 2B, the SRAM cell 205 includes a pair of pass-gate DDC transistors 225 and 230, a pair of pull-up DDC transistors 235 and 240, and a pair of pull-down DDC transistors 245 and 250. The pass-gate DDC transistors 225 and 230, and the pull-down DDC transistors 245 and 250 are typically n-channel (referred to herein as NMOS) transistors. The pass-gate DDC transistors 225 and 230 couple a pair of data lines BL0 and BLN0, also referred to as “bit lines”, to storage nodes SN1 and SN2 respectively, where the voltages at nodes SN1 and SN2 are inversely related. The pull-down DDC transistors 245 and 250 couple a power supply VSS, usually the ground voltage of the circuit, to the storage nodes SN1 and SN2 respectively. The pull-up DDC transistors 235 and 240 are typically p-channel (referred to herein as PMOS) transistors that couple the positive power supply VDDCOL0 to the storage nodes SN1 and SN2 respectively. The substrates of the NMOS transistors can be coupled to a power supply voltage VBNCOL0, and the substrates of the PMOS transistors can be connected to a power supply voltage VBPCOL0, if a substrate bias voltage is applied to the NMOS and PMOS transistors respectively.

SRAM cell 210 is similar to SRAM cell 205, and includes a pair of pass-gate DDC transistors 255 and 260, a pair of pull-up DDC transistors 265 and 270, a pair of pull-down DDC transistors 275 and 280, storage nodes SN3 and SN4, bit lines BL1 and BLN1, and power supplies VDDCOL1 and VBPCOL1. In certain embodiments, the n-channel body bias voltages VBNCOL0 and VBNCOL1 can be the same, such that all the n-channel body bias voltages can be connected to the same power supply voltage. In alternative embodiments, the p-channel body bias voltages VBPCOL0 and VBPCOL1 can be the same, such that all the p-channel body bias voltages can be connected to the same power supply voltage.

In FIG. 2B each column of the SRAM 200-B includes a column power supply block that supplies the power supply voltage for the corresponding column. The column power supply block 215 supplies the body bias voltages VBPCOL0, VBNCOL0, and the power supply voltage VDDCOL0. The column power supply block 220 supplies the body bias voltages VBPCOL1, VBNCOL1, and power supply voltage VDDCOL1. Each column power supply block independently controls the power supply voltage VDDCOL0/1, PMOS pull-up transistor body bias voltage VBPCOL0/1, and the NMOS transistor body-bias voltage VBNCOL0/1 supplied to each column such that each column can receive different power supply and body bias voltages. In addition, the column power supply block can provide different power supply voltages and body bias voltages to a given column at different times, or during different modes of operation.

The SRAM cell shown in FIG. 2B can retain its state indefinitely as long as the power supply voltage (VDDCOL0/1) is sufficient to operate the cell correctly, i.e., the power supply voltage exceeds some V_DDmin. The SRAM cell 205 includes two cross-coupled inverters consisting of the pair of transistors 235 and 245, and 240 and 250. The two inverters operate to reinforce the stored charge on storage nodes SN1 and SN2 continuously, such that the voltages at each of the two storage nodes are inverted with respect to one another. When SN1 is at a logical “1”, usually a high voltage, SN2 is at a logical “0”, usually a low voltage, and vice versa.

Referring to FIG. 2B, a write operation can be performed to store data in a selected SRAM cell, and a read operation can be performed to access stored data in a selected SRAM cell. In one embodiment, data is stored in a selected SRAM cell, e.g. SRAM cell 205, during a write operation by placing complementary write data signals on the two bit lines BL0 and BLN0, and placing a positive voltage (VWL) on the word line WL connected to the gate of the pass-gate transistors 225 and 230, such that the two bits lines BL0/BLN0 are coupled to the storage nodes SN1 and SN2, respectively. The write operation is successful when the write data signals on the two bit lines overcome the voltages on the two storage nodes (if they are at opposite states to the write data) and modify the state of the SRAM cell. The cell write is primarily due to the bit line driven low overpowering the opposing PMOS pull-up transistor via the pass-gate transistor (e.g., 240 being overpowered by BL0 via pass-gate 225). Thus, the relative strength ratio of the NMOS pass-gate transistor to the corresponding PMOS pull-up transistor can be important to maximizing the write margin.

In some embodiments, data is accessed from a selected SRAM cell, e.g. SRAM cell 205, during a read operation by precharging the two bit lines BL0 and BLN0 to a positive voltage, such as the positive power supply voltage VDDCOL0, and placing a positive voltage VWL on the word line WL such that the pass-gate transistors 225 and 230 allow the storage nodes SN1 and SN2 to be coupled to the bit lines BL0 and BLN0, respectively. During the read operation the SRAM cell 205 drives complementary read data signals onto the bit lines BL0 and BLN0, and a resulting read current pulls one of the two bit lines low in accordance with the stored state of the SRAM cell 205. The differential voltage on the bit lines BL0 and BLN0 can be sensed using a differential sense amplifier (not shown) that senses and amplifies the differential voltage signal on the bit lines. The output of the sense amplifier is subsequently output as the read data for the selected SRAM cell.

Embodiments of SRAM cells using DDC transistors can have enhanced performance characteristics as compared to SRAM cells using conventional MOSFETs.

Some of the reasons for the enhanced performance characteristics are (1) the DDC transistors can have lower threshold voltage variation, i.e., lower σV_T, and (2) the DDC transistors have higher I_eff and higher body coefficient. As a result, SRAM cells using DDC transistors can be designed more aggressively, in other words, with tighter design corners compared with the design corners using conventional MOSFETs. SRAM cells using DDC transistors can therefore be reliably designed to have (1) enhanced read stability that can be measured as enhanced read static noise margin, as well as lower SRAM minimum operating voltage V_DDmin; (2) enhanced write margin; (3) faster SRAM operation resulting from lower read current variability; all while enjoying (4) lower SRAM cell leakage.

FIG. 3A shows a hybrid SRAM 300 having hybrid SRAM cells (305 and 310) that use both DDC transistors and legacy transistors, in accordance with one embodiment. The SRAM cell 305 uses a pair of legacy PMOS transistors 335 and 340 as pull-up transistors. The SRAM cell 305 also uses a pair of DDC NMOS transistors 345 and 350 as pull-down transistors, and a pair of DDC NMOS transistors 325 and 330 as pass-gate transistors. SRAM cell 305 includes storage nodes SN1 and SN2, which are coupled to data lines BLN0 and BLN1 using the pass-gate DDC NMOS transistors 325 and 330.

SRAM cell 310 is similar, and includes a pair of pass-gate DDC NMOS transistors 355 and 360, a pair of pull-up legacy PMOS transistors 365 and 370, and a pair of pull-down DDC NMOS transistors 375 and 380. SRAM cell 310 includes storage nodes SN3 and SN4, which are coupled to data lines BL1 and BLN1 using the pass-gate DDC NMOS transistors 355 and 360.

Column power supplies 315 and 320 can provide various voltages to columns that include SRAM cells 305 and 310, respectively. Such voltages can include high power supply voltages VDDCOL0/1, n-channel body bias voltages VBNCOL0/1, and p-channel body bias voltages VBPCOL0/1. Power supplies 315/320 can be coupled to the substrates of the legacy PMOS transistors 335/340 and 365/370, respectively, if a substrate bias voltage (VBPCOL0/1) is applied to these transistors. Power supplies 315/320 can be coupled to the substrates of the DDC NMOS transistors 325/345/350 and 355/375/380, respectively, if a substrate bias voltage (VBNCOL0/1) is applied to these transistors. The sizing of transistors in an SRAM cell can be determined by a tradeoff between sizing for read static noise margin (SNM) and sizing for write margin. Using DDC transistors in an SRAM cell can improve both the read SNM and write margin for the SRAM cell.

Hybrid SRAM cells 305 and 310 have enhanced performance characteristics because of the DDC NMOS transistor characteristics. The DDC NMOS transistors can exhibit a higher current drive as compared to conventional MOSFETs, when a low voltage is being applied to the gate and the drain to source voltage is less than VGS−Vt of the transistor, i.e., such that the transistor is operating in the linear region. The drain to source voltage on DDC NMOS pull-down transistors of the hybrid SRAM cell is diminished during a read operation, e.g., at full VDD=1.0 V, this voltage can be lower than 0.2 V in certain embodiments. This voltage can be lower than 0.1 volts in certain alternative embodiments or at reduced VDD operation. Therefore, the higher current drive of the DDC NMOS transistors contributes to an enhanced Read SNM. In addition, during read operations, the DDC NMOS pass gate transistor of the hybrid SRAM cell has an increased body bias voltage that results from the rise in the storage node voltage during the read operation. Therefore, the enhanced body coefficient of the DDC NMOS transistor results in a DDC NMOS pass gate transistor with reduced current drive capability. The combination of the enhanced drive capability of the pull down transistor, and the reduced drive capability of the pass gate transistor results in an increased read SNM and increased cell stability. This is evident qualitatively from the better voltage divider ratio obtained by weakening the pass gate DDC NMOS transistor and strengthening the pull down DDC NMOS transistor, respectively, since the current drive is not reduced on a write, when the bit line BL is driven to or near VSS to write the cell. Additional benefits of using DDC transistors in SRAM cells are discussed in pending U.S. patent application Ser. No. 13/471,353 filed May 14, 2012, titled Integrated Circuit Devices and Methods, the entirety of which disclosure is incorporated herein by reference.

For the hybrid SRAM cells 305 and 310 shown in FIG. 3A, using DDC NMOS pass-gate and DDC NMOS pull-down transistors provides increased read SNM, and therefore, a lower read failure rate. In addition, since the DDC NMOS transistors have a lower variability of threshold voltage, i.e., lower σVT and lower transistor matching coefficient AVT, the hybrid SRAM cells 305 and 310 can have a lower VDDmin than a conventional SRAM cell that uses similarly sized conventional NMOS and PMOS transistors.

FIG. 3B shows a hybrid SDC SRAM 301 having hybrid SDC SRAM cells (306 and 311) that used both SDC transistors and legacy transistors, in accordance with one embodiment. The SRAM cell 306 uses a pair of SDC NMOS transistors 346 and 351 as pull-down transistors, and a pair of SDC NMOS transistors 326 and 331 as pass-gate transistors. The SRAM cell 306 also uses a pair of legacy PMOS transistors 335 and 340 as pull-up transistors. SRAM cell 311 is similar, and includes a pair of pass-gate SDC NMOS transistors 356 and 361, a pair of pull-down SDC NMOS transistors 376 and 381, and a pair of pull-up legacy PMOS transistors 365 and 370.

A hybrid SDC SRAM cell 306/311 can have enhanced performance characteristics compared with SRAM using conventional transistors because of the SDC transistor characteristics. These improved transistor characteristics are similar to the enhanced characteristics of a hybrid SRAM cell using DDC and legacy transistors (e.g., FIG. 3A), and therefore can be designed to tighter design corners compared with conventional MOSFETs, to result in performance benefits such as, increased read SNM, increased cell stability, lower read and write failure rates, and lower VDDmin. Using SDC transistors in an SRAM cell can improve both the read SNM and write margin for the SRAM cell.

Referring to FIGS. 3A and 3B, each column of the SRAMs 300 and 301 can include a column power supply 315/320 that supplies a power supply voltage (VDDCOL0/1) for the corresponding column. As understood from above, column power supplies 315/320 can also provide body bias voltages to one or both types of transistors in an SRAM cell. In the particular embodiment of FIGS. 3A and 3B, in addition to power supply VDDCOL0, column power supply 315 can provide n-channel body bias voltage VBNCOL0 and p-channel body bias voltage VBPCOL0. Similarly, in addition to power supply VDDCOL1, column power supply 320 can provide n-channel body bias voltage VBNCOL1 and p-channel body bias voltage VBPCOL1. In certain embodiments, the n-channel body bias voltages VBNCOL0 and VBNCOL1 can be the same, such that all the n-channel body bias voltages can be connected to the same power supply voltage. In alternative embodiments, the p-channel body bias voltages VBPCOL0 and VBPCOL1 can be the same, such that all the p-channel body bias voltages can be connected to the same power supply voltage.

Column power supplies 315 and 320 can either be same or different. That, column power supplies 315/320 can operate together to provide power supply and/or body bias voltages, or each column power supply can independently control its power supply voltage and/or body bias voltage(s). In addition, in some embodiments the column power supplies 315/320 can provide different power supply voltages and/or body bias voltages to the same column at different times, or during different modes of operation. For example, the column power supplies 315/320 can generate power supply and body bias voltages that are identical for read and write operations, or they can generate voltages that are different for read and write operations, depending on the embodiment.

In addition to the hybrid SRAM cell and the hybrid SDC SRAM cells described above, alternative embodiments of hybrid SRAM cells that use two or more different types of transistors can also provide better performance characteristics. Such embodiments can include SRAM cells that use both DDC and SDC transistors. In addition, embodiments that include SDC SRAM cells that use only SDC transistors can also provide similar advantages.

In certain embodiments, transistor body bias voltages (e.g., VBNCOL0/1, VBPCOL0/1) can be applied globally, i.e., to the entire integrated circuit, or to all devices in the SRAM arrays, as well as by column as shown, in order to allow precise electrically controlled targeting of the leakage and other SRAM characteristics. The enhanced body effect of the DDC and SDC transistors facilitates such wider use of body bias compared to conventional MOSFETs. In alternative embodiments, the body bias voltages can be applied to only one of the transistors types in the integrated circuit or the SRAM array. For example, the body bias voltages can be applied to only the PMOS transistors, or to only the NMOS transistors in the integrated circuit or the SRAM array. In addition, the body bias voltages applied to the integrated circuit or the SRAM array can either be fixed throughout the IC operation and/or lifetime, or may be varied dynamically in order to meet target operational characteristics of the SRAM as described below. This electrically controlled targeting of the leakage and other SRAM device characteristics can be used either alone or in combination with additional adjustments that can be obtained due to the structure and processing of the specific transistors and/or the operating conditions of the transistors.

FIG. 3C shows read and write failure rates for an SRAM cell at different stages of the design process to reduce VDDmin, in accordance with one embodiment. Four sets of read and write failure rates are shown in FIG. 3C corresponding to four SRAM cells—(1) a baseline SRAM cell with substantially balanced read and write failure rates; (2) a SRAM cell with 20% AVT improvement for the NMOS transistors; (3) a SRAM cell with 30% AVT improvement for the NMOS transistors; and (4) a SRAM cell with the PMOS threshold voltage increased by 35 mV and a 30% AVT improvement for NMOS. FIG. 3C also shows the VDDmin for each of these SRAM cells.

In one embodiment, the baseline SRAM cell can be a SRAM cell implemented using legacy PMOS and NMOS transistors only, and the SRAM cells with improved NMOS AVT can be hybrid SRAM cells that use NMOS DDC transistors and PMOS legacy transistors as described with reference to FIG. 3A above. The pass-gate, pull-up, and pull-down transistors of the hybrid SRAM cells have approximately the same drawn sizes as corresponding transistors of the baseline cell.

FIG. 3C shows that the baseline SRAM cell can be designed to operate at a lower VDDmin by converting it to a hybrid SRAM cell, where the NMOS transistors in the baseline SRAM cell are substituted with NMOS DDC transistors with improved AVT. Improving the NMOS AVT for the SRAM can improve the read SNM and write margin for a predetermined value of the power supply voltage VDD, resulting in lower read and write failures, and a lower VDDmin. FIG. 3C also shows that as VDDmin is reduced, the rates at which read failures and write failures increase can differ, and therefore, the SRAM cell can become either read limited (i.e., read failure rate higher than the write failure rate) or write limited (write failure rate higher than the read failure rate). For example, FIG. 3C shows that the SRAM cells with 20% and 30% NMOS AVT improvement are write limited at a VDDmin of 0.72V and 0.69V respectively. It is noted that if the hybrid SRAM cell obtained by converting the baseline SRAM cell has a read and write failure rate that is sufficiently low to provide a desired yield, the design method described herein can provide an improved target SRAM cell that has a lower VDDmin, without providing further reductions in the read and/or write failure rates. This can be observed in FIG. 3C, where the design method results in write failure rates for 3C(1) and 3C(4) that are substantially identical, but results in a VDDmin reduction of approximately 0.1V (i.e. from 0.77V to 0.67V). However, in alternative embodiments, where the hybrid SRAM cell obtained from converting the baseline SRAM cell has read and write failure rates that exceed a desired failure rate, the design method described herein can provide an improved target SRAM call having an acceptable (i.e., less that the target) failure rate as well as a lower VDDmin.

With reference to FIG. 3C, a read or write limited SRAM cell can be further designed to operate at a lower VDDmin by retargeting the PMOS and/or the NMOS threshold voltage. For example, the SRAM cell corresponding to a VDDmin of 0.69V ((3) in FIG. 3C) can be designed by way of weakening the legacy PMOS pull-up transistors, i.e., by increasing the PMOS threshold voltage, resulting in further reduction of VDDmin. In other embodiments, the SRAM cell can also be designed by way of retargeting the threshold voltage of the NMOS transistors in the SRAM cell. As shown in FIG. 3C, increasing the PMOS threshold voltage can provide a balanced SRAM cell that has substantially similar read and write failure rates since the read failure rate can increase and the write failure rate can decrease with increases in the PMOS threshold voltage. However, the total cell failure rate is reduced. This also reflects a lower failure rate for the current power supply voltage at which these failure rates are measured, and therefore, the VDDmin for the SRAM can be reduced further at the required or desired yield.

Some embodiments of the hybrid SRAM cell using DDC NMOS transistors (for the pull-down and pass-gate transistors) and legacy PMOS pull-up transistors can use only one type of gate metal (i.e., the legacy PMOS transistor gate metal). A single metal hybrid SRAM cell can require fewer processing steps and mask layers for fabrication, and therefore, it can have a higher yield than a SRAM cell that requires the use of two different gate metals for the NMOS and PMOS transistors. The NMOS DDC transistor can be advantageously used in the single metal hybrid SRAM cell because the threshold voltage of the DDC transistor can be set by the screening region dopant concentration, the threshold set region dopant concentration, and the thickness of the epitaxial layer, as discussed above. Therefore, the threshold voltage of the DDC NMOS transistor can be set to a desired target value even though the gate metal that is used is the PMOS gate metal having a PMOS workfunction. Similar embodiments of the hybrid SDC SRAM cell can be implemented using a single gate metal, and can provide similar advantages.

Various methods in accordance with the embodiments discussed below can be used to generate a target SRAM cell based on a source SRAM cell, where the target SRAM cell is a hybrid SRAM that uses DDC NMOS transistors or SDC NMOS transistors, and the source SRAM cell uses conventional MOSFETs, e.g., MOSFETs having dopants in the channel and/or halo implants. In one embodiment, the target SRAM cell is designed to be a drop-in replacement for the source SRAM cell. The target SRAM cell can have the same area as the source SRAM cell, and each of the DDC/SDC transistors in the target SRAM cell can have the same size as the corresponding transistor in the source SRAM cell. In alternative embodiments, the target SRAM cell can be fabricated without making any modifications to the Graphic Data System (GDS) format information corresponding to the source SRAM cell. In other embodiments, the target SRAM cell can be fabricated using the same GDS format information as the source SRAM cell but the GDS information can be resized to produce the master or direct write information for the migrated SRAM cell.

FIG. 4A illustrates a flow diagram of a method 400 for designing a target SRAM cell based on a source SRAM cell, for which the NMOS and PMOS threshold voltages are retargeted, where the target SRAM cell has a lower VDDmin than the source SRAM cell, in accordance with one embodiment. In one embodiment, VDDmin can be determined as the lowest value of VDD at which all, or a predetermined percentage of the SRAM cells can function properly for both read and write operation, i.e. the SRAM cells have sufficient read SNM, read current, and write margin. The method 400 designs the NMOS and PMOS transistor threshold voltages (hereinafter referred to as “V_TN” and “V_TP” respectively) of the transistors in the source SRAM cell to obtain the target SRAM cell.

Step 405 determines relevant characteristics of the source SRAM cell including the size of one or more transistors in the source SRAM cell, as well as the threshold voltages V_TN and V_TP of the NMOS and PMOS transistors in the source SRAM cell. Step 405 can also determine additional parameters for the transistors in the source SRAM cell, e.g., the threshold voltage variation characterized by AVT or σVT, drain induced barrier lowering (DIBL), drive current, leakage current, etc. In addition, step 405 determines the VDDmin of the source SRAM cell. The source SRAM cell can be any SRAM cell, including the SRAM cell embodiments discussed above with reference to FIGS. 3A/B.

Step 410 determines the new SRAM cell failure rates in response to changing either one or both the threshold voltages V_TN and V_TP, when the SRAM cell is operating at a high power supply voltage of VDDmin. The SRAM cell failure rate can be determined as the read and write failure rates at the power supply voltage VDDmin currently under evaluation. In various embodiments, during step 410 the failure rates are calculated for a number of candidate V_TN and V_TP points during step 410 that correspond to one or more of the following changes to V_TN and V_TP:

(a) V_TN+ΔV_T, V_TP;

(b) V_TN+ΔV_T, V_TP+ΔV_T;

(c) V_TN, V_TP+ΔV_T;

(d) V_TN−ΔV_T, V_TP+ΔV_T;

(e) V_TN−ΔV_T, V_TP;

(f) V_TN−ΔV_T, V_TP−ΔV_T;

(g) V_TN, V_TP−ΔV_T, and

(h) V_TN+ΔV_T, V_TP−ΔV_T.

FIG. 4B is a graph showing a range of candidate V_TN and V_TP points with reference to current starting point V_TN and V_TP, when the method of FIG. 4A is implemented. In certain alternative embodiments, the failure rates can be determined at fewer than the eight points shown in the figure. For example, the failure rates can be determined for candidate V_TN and V_TP corresponding to only the corners (i.e. points b, f, d, and h in FIG. 4B), or only the edges (i.e. points a, c, e, and g). In one embodiment, the value of the step size ΔV_T can be fixed, e.g. it can be set at 5 mV. In alternative embodiments, a variable step size can be used, where a large step can be used initially, and the step size can be reduced as the impact of changing V_T on the failure rate shows that large steps may not allow further optimization of the SRAM cell within the failure limit and failure criterion. Therefore, if the failure rates corresponding to the candidate V_TN and V_TP are higher than the current failure rate (at V_TN and V_TP), then the step size can be reduced, and the response of the SRAM cell can be determined for the reduced step size. Thus, the (V_TN, V_TP) space can initially be traversed more quickly, allowing a faster and more efficient design for an SRAM cell. In other embodiments, the step size can be varied as needed using alternative algorithms that can reduce the number of iterations required to arrive at the new target SRAM cell.

Referring back to FIG. 4A, step 415 analyzes the SRAM cell failure rates obtained in step 410 to determine if any of the failure rates corresponding to the candidate V_TN and V_TP points in step 410 are lower than the failure rate at (V_TN, V_TP), and if leakage and other performance constraints are satisfied. If one or more of the failure rates corresponding to the candidate V_TN and V_TP are lower (branch 460 labeled Y) and at least one of these candidate (V_TN, V_TP) points satisfy the leakage and performance constraints, execution of the method 400 continues to step 420. Otherwise execution proceeds along branch 465 labeled “N”, and execution of the method 400 continues to step 425. In one embodiment, step 415 determines whether the leakage constraints are satisfied by determining whether the leakage current for the SRAM cell with the candidate V_TN and V_TP is less than a predetermined maximum leakage current at a nominal or maximum value of the power supply voltage VDD. Similarly, step 415 can determine whether other performance characteristics are satisfied at a nominal or maximum value of the power supply voltage VDD. In certain embodiments, candidate (V_TN, V_TP) points that have been evaluated and rejected during steps 410 and 415, i.e., candidate (V_TN, V_TP) points rejected in favor of a candidate (V_TN, V_TP) point having a lower failure rate, are stored such that these candidate points are evaluated only once during successive steps of the design method 400.

With reference to step 415, in certain embodiments, reducing V_TN and/or V_TP can reduce VDDmin but the read/write failure rates can change. The impact of reducing V_TN and/or V_TP on the read/write failure rates can be dependent on the state of the SRAM cell before the threshold voltages are changed, and whether the SRAM cell is read limited, write limited, or balanced prior to changing the threshold voltages. Reducing V_TN and V_TP can increase the leakage. However, the leakage can be reduced by using transistors with improved AVT that can reduce the average cell leakage, which is proportional to the SRAM array leakage (the leakage that impacts the integrated circuit). Therefore, SRAM arrays using DDC transistors can have a lower leakage at the same V_TN and V_TP. However, the increasing leakage can still limit the SRAM operating range as it limits the range of V_TN and V_TP that can be used. In addition, increasing V_TN can reduce the read current Iread thereby reducing read performance. However, improving the AVT can reduce the impact of read current degradation as well.

Step 420 modifies V_TN and V_TP of the SRAM cell to improve the failure rate, and determines the failure rate of the modified SRAM cell. In one embodiment, step 420 can analyze the response of the SRAM cell to the candidate V_TN and V_TP in step 410 described above and can select a new V_TN and V_TP in accordance with one of the following approaches:

Select the V_TN and V_TP modification (from the candidate V_TN and V_TP points analyzed in step 410 above) that results in the SRAM cell having balanced read and write failures, i.e., the read failure rate being substantially similar to the write failure rate.

In an alternate embodiment of method 400, step 420 moves the point under analysis for the SRAM cell failure rates towards candidate V_TN and V_TP that result in the read failure rate being substantially similar to the write failure rate (i.e., the read or write SRAM failure rates may not be calculated for all of the eight possible candidate V_TN and V_TP points listed for step 410 above), and step 415 selects the candidate V_TN and V_TP point that results in the SRAM cell having more balanced read and write failures.

Select a new V_TN and V_TP (from the candidate points analyzed in step 410 above) that result in the SRAM cell having minimum total failure rate. In one embodiment, the total failure rate of the SRAM cell can be the sum of the read failure rate and the write failure rate. In an alternative embodiment, the total failure rate can be the maximum failure rate, which is the higher of the read failure rate and the write failure rate.

Step 425 compares the failure rate of the SRAM cell to a predetermined maximum allowed failure rate. If the failure rate is less than the maximum allowed failure rate, execution of method 400 continues along branch 470 (labeled “Y”), the current values of VDDmin, V_TN, and V_TP are saved (step 430), control is transferred to step 435 and further iterations within the design process are performed as illustrated in the flow diagram of method 400. If the failure rate is greater than the maximum allowed failure rate, execution of method 400 continues along branch 475 (labeled “N”), control is transferred to step 440.

Step 435 reduces VDDmin by a predetermined amount ΔVDD, and transfers control to step 410 for continued design of the SRAM cell. In one embodiment, the value of the step size ΔVDD can be fixed, e.g. it can be set at 5 mV. In alternative embodiments, a variable step size can be used, where a large step can be used initially, and the step size can be reduced as the impact of changing VDD on the failure rate shows that large steps may not allow further modification of the design of the SRAM cell within the failure limit and failure criterion. Therefore, if the failure rates corresponding to the modified VDD are higher than the current failure rate (at the saved VDD), then the step size can be reduced, and the response of the SRAM cell can be determined for the reduced step size. Thus, the VDD range can initially be traversed more quickly, allowing for a faster design method that arrives to substantially the same optimized SRAM cell in fewer design steps. In other embodiments, the VDD step size can be varied using alternative algorithms that can reduce the number of iterations required to arrive at the new target SRAM cell.

Referring to step 425, if the failure rate is greater than the maximum allowed failure rate, execution of the method 400 continues along branch 475 (labeled “N”), the saved values of VDDmin, V_TN, and V_TP are recovered (step 440), and the target SRAM cell is obtained (step 445).

In alternative embodiments of the method 400, if none of the modified (V_TN, V_TP) points analyzed during step 425 satisfy the conditions of having a lower failure rate as well as the predetermined leakage and performance constraints, the substrate bias voltage for the DDC NMOS transistors can be changed by a step size ΔV_BN and the resulting failure rates, leakage, and performance characteristics are reevaluated. The substrate bias voltage for the NMOS DDC transistor can be increased until one or more of the modified (V_TN, V_TP) points satisfy the failure rate, leakage, and performance constraints. In other embodiments of the method 400, the substrate bias voltage for only the PMOS transistors, only the NMOS transistors, or both the PMOS and NMOS transistors, can be either increased or decreased until the SRAM cell satisfies the failure rate, leakage, and performance constraints.

FIG. 5A is a contour plot 500 showing bit failure rates for a fixed VDD (0.7V), and a possible sequence of V_TN and V_TP offsets that can be traversed in order to obtain a target SRAM cell. The trajectory 505 illustrates a possible sequence of V_TN and V_TP offsets that can be traversed during the design of the SRAM cell by one of the method embodiments described above. The trajectory 505 starts at an initial offset of (0, 0) corresponding to the source SRAM with no modifications to V_TN and V_TP. The end point of the trajectory 505 represents the offsets or modifications to V_TN and V_TP that provide a target SRAM cell for VDD of 0.7V.

FIG. 5B is a contour plot 510 of bit failure rates of the target SRAM cell obtained at VDD of 0.7V, when VDD is reduced to 0.69V. The trajectory 515 shows a possible sequence of V_TN and V_TP offsets that can be traversed in order to obtain a design for a target SRAM cell at VDD of 0.69V. If the failure rate of the target SRAM cell at 0.69V VDD (corresponding to the end point of the trajectory 515) is less than the maximum allowed failure rate, and if leakage and other performance characteristics are satisfied, VDD can be reduced further and the design process can be continued, in accordance with the method embodiments described above.

The various methods for designing the SRAM cell described above can be used to set the transistor W/L and/or the threshold voltages V_TP and V_TN for the transistors used in the target SRAM cell to design the SRAM with reduced VDDmin. In one embodiment, the transistor W/L can be modified as part of the design such that no GDS changes are required, i.e. the transistor changes are made within a range that can be obtained by performing an optional GDS resizing. In addition, embodiments of the methods described above can be used to retarget the SRAM cell when the electrical parameters or characteristics of any of the transistors used in the SRAM cell are modified. Embodiments of the methods described above can be used to retarget SRAM cells using only legacy transistors, only DDC transistors, only SDC transistors, as well as hybrid SRAM cells, and hybrid SDC SRAM cells.

Together, the structures and methods of making the structures allow for DDC or SDC transistors having an enhanced body coefficient as compared to conventional nanoscale devices. Thus, the response of the DDC/SDC transistor can vary within a wider range to a change in the body bias voltage applied to the screening region. More specifically, the enhanced body coefficient of the DDC/SDC transistor can allow a broad range of ON-current and OFF-current that depends on the body bias voltage applied to the screening region, as compared to the body bias voltage applied to a conventional device. In addition, the DDC/SDC transistors have a better AVT, i.e., a lower σV_T than conventional devices. The lower σV_T provides a lower minimum operating voltage VDD and a wider range of available nominal values of V_T. The enhanced body coefficient of the DDC/SDC transistor can also allow a broad range of threshold voltage that depends on the body bias voltage applied to the screening region, as compared to the body bias voltage applied to a conventional device. The screening region allows effective body biasing for enhanced control of the operating conditions of a device or a group of devices to be set by controlling the applied body bias voltage. In addition, different operating conditions can be set for devices or groups of devices as result of applying different body bias voltages.

As will be understood, wafers and die supporting multiple transistor types, including those with and without the described dopant layers and structures are contemplated. Electronic devices that include the disclosed transistor structures or are manufactured in accordance with the disclosed processes can incorporate die configured to operate as “systems on a chip” (SoC), advanced microprocessors, radio frequency, memory, and other die with one or more digital and analog transistor configurations, and are capable of supporting a wide range of applications, including wireless telephones, communication devices, “smart phones”, embedded computers, portable computers, personal computers, servers, and other electronic devices. Electronic devices can optionally include both conventional transistors and transistors as disclosed, either on the same die or connected to other die via motherboard, electrical or optical interconnect, stacking or through used of 3D wafer bonding or packaging. According to the methods and processes discussed herein, a system having a variety of combinations of analog and/or digital transistor devices, channel lengths, and strain or other structures can be produced.

It should be appreciated that in the foregoing description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure aiding in the understanding of one or more of the various inventive aspects. This method of disclosure, however, is not to be interpreted as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention.

It is also understood that the embodiments of the invention may be practiced in the absence of an element and/or step not specifically disclosed. That is, an inventive feature of the invention may be elimination of an element.

Accordingly, while the various aspects of the particular embodiments set forth herein have been described in detail, the present invention could be subject to various changes, substitutions, and alterations without departing from the spirit and scope of the invention.