SUVOLTA, INC.

Semiconductor structure with substitutional boron and method for fabrication thereof

Multiple VDD clock buffer

Ring oscillator with NMOS or PMOS variation insensitivity

SRAM performance monitor

Circuits and devices for generating bi-directional body bias voltages, and methods therefor

Electronic device with controlled threshold voltage

Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer

Tipless transistors, short-tip transistors, and methods and circuits therefor

Transistor having reduced junction leakage and methods of forming thereof

Process for manufacture of integrated circuits with different channel doping transistor architectures and devices therefrom

SRAM cell layout structure and devices therefrom

Circuits and methods for measuring circuit elements in an integrated circuit device

Analog transistor

Memory circuits and methods of making and designing the same

Body bias circuits and methods

Integrated circuit devices and methods

Porting a circuit design from a first semiconductor process to a second semiconductor process

Monitoring and measurement of thin film layers

Method for substrate preservation during transistor fabrication

Source/drain extension control for advanced transistors

Electronic device with controlled threshold voltage

Process for manufacturing an improved analog transistor

CMOS gate stack structures and processes

Dynamic random access memory (DRAM) with low variation transistor peripheral circuits

Tools and methods for yield-aware semiconductor manufacturing process target generation

Deeply depleted MOS transistors having a screening layer and methods thereof

Electronic devices and systems, and methods for making and using the same

Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer

Reducing or eliminating pre-amorphization in transistor manufacture

Semiconductor structure and method of fabrication thereof with mixed metal types

Porting a circuit design from a first semiconductor process to a second semiconductor process

Source/drain extension control for advanced transistors

CMOS structures and processes based on selective thinning

Low power semiconductor transistor structure and method of fabrication thereof

Circuits and methods for measuring circuit elements in an integrated circuit device

Reducing or eliminating pre-amorphization in transistor manufacture

Source/drain extension control for advanced transistors

Analog circuits having improved transistors, and methods therefor

Digital circuits having improved transistors, and methods therefor

Electronic devices and systems, and methods for making and using the same

Electronic devices and systems, and methods for making and using the same

Circuit devices and methods having adjustable transistor body bias

Electronic devices and systems, and methods for making and using the same

Analog circuits having improved transistors, and methods therefor

Semiconductor structure with improved channel stack and method for fabrication thereof

Source/drain extension control for advanced transistors

Method for minimizing defects in a semiconductor substrate due to ion implantation

Method for minimizing defects in a semiconductor substrate due to ion implantation

Method for reducing punch-through in a transistor device

Semiconductor structure and method of fabrication thereof with mixed metal types

Transistor with threshold voltage set notch and method of fabrication thereof

Junction field effect transistor having a double gate structure

Low power semiconductor transistor structure and method of fabrication thereof

Method for providing temperature uniformity of rapid thermal annealing

Method and apparatus for improving SRAM write operations

Advanced transistors with punch through suppression

Junction field effect transistor (JFET) structure having top-to-bottom gate tie and method of manufacture

Electronic devices and systems, and methods for making and using the same

Circuit configurations having four terminal devices

Semiconductor device with multiple transistors formed in a partially depleted semiconductor-on-insulator substrate

Method and apparatus for improving SRAM write operations

Memory cell including an emitter follower and emitter follower sensing scheme and method of reading data therefrom

Voltage-level translator

Current-limited output buffer

Advanced JFET with reliable channel control and method of manufacture

Method for manufacturing a junction field effect transistor having a double gate

JFET device with improved off-state leakage current and method of fabrication

Level-shifting circuit with bipolar junction transistor

Junction field effect transistor using a silicon on insulator architecture

Integrated circuit using complementary junction field effect transistor and MOS transistor in silicon and silicon alloys

Programmable switch circuit and method, method of manufacture, and devices and systems including the same

System and method for routing connections with improved interconnect thickness

Circuit configurations having four terminal JFET devices

Semiconductor device, design method and structure

System and method for routing connections

Swapped-body RAM architecture

Method of forming an oxide isolated metal silicon-gate JFET

Transistor providing different threshold voltages and method of fabrication thereof

Dynamic random access memory having junction field effect transistor cell access device

Integrated circuit using complementary junction field effect transistor and MOS transistor in silicon and silicon alloys

Self aligned gate JFET structure and method

Common data line signaling and method

Semiconductor device including a bias voltage generator

Semiconductor device storage cell structure, method of operation, and method of manufacture

Image sensing cell, device, method of operation, and method of manufacture

Semiconductor device having a fin structure and fabrication method thereof

Double gate JFET with reduced area consumption and fabrication method therefor

Content addressable memory cell including a junction field effect transistor

Circuit and method for generating electrical solutions with junction field effect transistors

Junction field effect transistor input buffer level shifting circuit