Data storage assembly for archive cold storage

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. application Ser. No. 14/023,386, filed Sep. 10, 2013, which claims the benefit of U.S. Provisional Application No. 61/818,287, filed May 1, 2013, both of which are hereby incorporated by reference in their entirety.

BACKGROUND

Data centers can provide cloud storage systems to remotely store data for networked systems. However, such cloud storage systems can consume large amounts of power at the data center to store and manage data in an array of data storage devices (DSDs).

“Cold storage” or archive storage generally refers to ways of providing more cost effective storage for rarely accessed data. The cost of storage is usually the most important metric, sacrificing time to data. Such cold storage can include powering only the DSD required for an active request for data. For example, the Open Compute specification calls for an Open Vault tray of 15 DSDs. Only one DSD in the tray is powered at a time, to reduce power, heat, and vibration. However, because only one DSD is powered at a time, the other inactive DSDs may include components which are not simultaneously needed or utilized, and may therefore be redundant while consuming excess power.

BRIEF DESCRIPTIONS OF THE DRAWINGS

The features and advantages of the implementations of the present disclosure will become more apparent from the detailed description set forth below when taken in conjunction with the drawings. The drawings and the associated descriptions are provided to illustrate implementations of the disclosure and not to limit the scope of what is claimed.

FIG. 1A presents a data storage rack according to an implementation of the present disclosure;

FIG. 1B presents a data storage tray according to an implementation of the present disclosure;

FIG. 1C presents a box diagram of a data storage tray according to an implementation of the present disclosure;

FIG. 2A presents a hard disk assembly (HDA) according to an implementation of the present disclosure;

FIG. 2B presents a conceptual diagram of an HDA according to an implementation of the present disclosure;

FIG. 2C presents an HDA connecting to a main board according to an implementation of the present disclosure;

FIG. 3 presents a single board implementation according to an implementation of the present disclosure;

FIG. 4A presents a top view of a single board implementation according to an implementation of the present disclosure;

FIG. 4B presents a main circuit board according to an implementation of the present disclosure;

FIG. 4C presents a main circuit board according to another implementation of the present disclosure;

FIG. 5A presents a block diagram of a data storage tray according to an implementation of the present disclosure;

FIG. 5B presents a diagram of a data storage tray with a bridge card according to an implementation of the present disclosure;

FIG. 6 presents a diagram of a board configured for distributed computing according to an implementation of the present disclosure; and

FIG. 7 presents a diagram of a board configured for distributed computing and a direct input according to an implementation of the present disclosure.

DETAILED DESCRIPTION

In the following detailed description, numerous specific details are set forth to provide a full understanding of the present disclosure. It will be apparent, however, to one of ordinary skill in the art that the various implementations disclosed may be practiced without some of these specific details. In other instances, well-known structures and techniques have not been shown in detail to avoid unnecessarily obscuring the various implementations.

While the description herein refers generally to a NAND flash memory, it is understood that other implementations can include one or more of various types of solid state memory such as Chalcogenide RAM (C-RAM), Phase Change Memory (PC-RAM or PRAM), Programmable Metallization Cell RAM (PMC-RAM or PMCm), Ovonic Unified Memory (OUM), Resistance RAM (RRAM), NAND memory (e.g., single-level cell (SLC) memory, multi-level cell (MLC) memory, or any combination thereof), NOR memory, EEPROM, Ferroelectric Memory (FeRAM), Magnetoresistive RAM (MRAM), spin-transfer torque RAM (STT-RAM), other discrete non-volatile memory (NVM) chips, or any combination thereof.

FIG. 1A presents a server rack 100, which may be used for cold storage. The server rack 100 includes a plurality of trays 150 for storing DSDs. FIG. 1B presents a tray 150. The tray 150 includes a plurality of DSDs 160, a drive-plane board 170, a Serially Attached SCSI (SAS) expander board 180, and an expander board 190. The tray 150 may follow the Open Compute specification for an Open Vault tray of 15 DSDs. Although the present disclosure discusses the Open Compute specifications, implementations of the present disclosure are not limited to the Open Compute specification and may be adapted to work with other specifications or applications.

The DSDs 160 may be a conventional drive, such as a hard disk drive (HDD), solid state drive (SSD), solid state hybrid drive (SSHD), or other DSD known in the art. The DSDs 160 are each connected to the drive-plane board 170, which may provide more mechanically reliable connections than cables. The drive-plane board 170 allows for connections to each individual DSD 160. For example, the SAS expander board 180 may be a plug-in card that connects to each DSD 160 through the drive-plane board 170. Because SAS is typically a point-to-point connection (i.e. a direct connection between a host system and a device), the SAS expander board 180 manages multiple direct or point-to-point connections to each DSD 160. Power flows through the drive-plane board 170. The expander board 190 may manage a fan (not shown) and power connections.

FIG. 1C presents a conceptual diagram of the tray 150. The expander board 190 includes a memory 140, a System-on-Chip (SoC) 130, a network interface 135, a plurality of SATA multipliers 110, and a drive plane board interface 120. The SoC 130 may include a processor as well as other components integrated into a single chip. The expander board 190 works in conjunction with a fan card 192 and a backplane card 194. Interfacing with 16 DSDs 160 is performed with at least 4 SATA multipliers 110, which can consume power, create heat, and increase manufacturing costs.

FIG. 2A illustrates a view of a hard disk assembly (HDA) 200 according to an implementation of the present disclosure. The HDA 200 includes a main device 201, a feed through connector 202 and a helium charge port 203. The HDA 200 may be a conventional drive, such as a hard disk drive (HDD), solid state drive (SSD), solid state hybrid drive (SSHD), or other DSD known in the art. In addition, the HDA 200 may be a modified DSD, as will be discussed below.

FIG. 2B presents a conceptual block diagram of the HDA 200. The HDA 200 includes a printed circuit board assembly (PCBA) or bridge board (or bridge card) 210, a platter 220, a head assembly 230, and a preamp 235 to reduce a Signal-to-Noise Ratio (SNR) for data read from platter 220. The HDA 200 may include an increased or decreased number of platters 220 than conventionally used. The bridge board 210 includes a preamp 211, a motor controller 212, a bridge 213, a first circuitry 214, and a second circuitry 215. The preamp 211 may further reduce a SNR for data read from platter 220. The first circuitry 214 and/or the second circuitry 215 may be a sensor, a power large-scale integrated circuit (PLSI), an emergency power off retract (EPOR), or other component. In alternative implementations, the bridge board 210 may include more or less of the above components, in that the components are optional.

The HDA 200 is a simplified disk drive without certain circuitry. Circuitry for functions such as a primary read channel, controller, host interface, and memory are moved to a shared circuit board, such as a shared bridge board 210 or a shared motherboard/main board (MB) 250 in FIG. 2C, to reduce redundant components. Because only one drive is powered on at a time, one instance of circuitry functions such as primary read channel, controller, host interface, and memory can be shared by the drives to reduce components, cost, heat, and power consumption.

FIG. 2C depicts one implementation of mounting the HDA 200 to the MB 250. The bridge board 210 further includes an HDA connector 240 and MB connector space 245. The MB 250 includes a MB connector 255.

The HDA 200 connects to the HDA connector 240 through, for example, the feed through connector 202. The HDA connector 240 and the feed through connector 202 may be interchanged or modified to match DSD design and assembly processes. The MB connector 255 connects to the MB connector space 245. The MB connector 255 and the MB connector space 245 may be similar to the HDA connector 240 and the feed through connector 202. Alternatively, the MB connector 255 and the MB connector space 245 may be an alternate or unique configuration to facilitate the preferred orientation and removability of the HDA 200. The bridge board 210 may be on a parallel plane as the MB 250 and the HDA 200. Alternatively, the bridge board 210 may be placed perpendicular to the MB 250, as an edge card.

FIG. 3 presents a conceptual diagram of a single board implementation, an MB 300. Rack connectors 340 provide host and power connections to the MB 300, specifically connecting a host to the SoC subsystem 310 and a 12V power connection to a power converter 350. Although FIG. 3 depicts a 12V power supply, in other implementations other appropriate power connections and voltages may be utilized.

The SoC subsystem 310 includes a clock 319, a flash memory 317, an SoC 311, a random-access memory (RAM) 313, and a regulator 315. The SoC 311 may include a processor as well as other circuitry integrated onto a single chip. The SoC subsystem 310 and/or the SoC 311 may serve as a controller and may perform other functions, such as error recovery for reading and writing data. The SoC subsystem 310 further interfaces with a multiplexer (mux) subsystem 320. The mux subsystem 320 includes a preamp mux 322 and a mux controller 324. The mux subsystem 320 connects to a bank 330, which includes a plurality of sensors 334. The sensors 334 may be PLSI sensors mounted in the same location as a production HDA circuit board, to ensure that accurate shock and vibration information is captured and communicated to the SoC subsystem 310. The mux subsystem 320 also controls a fan and cabinet services 360, which can include lights, fan control, and temperature reporting.

The MB 300 includes the plurality of sensors 334 to ensure better reliability by having a sensor 334 for each attached HDA (not shown in FIG. 3). In other implementations, the bank 330 may include more or less sensors 334. The mux subsystem 320 allows the plurality of sensors 334 to communicate with the SoC subsystem 310.

Because the HDAs are configured without their own individual hard disk controllers (HDC), the SoC subsystem 310 acts as the HDC, connected through the mux subsystem 320. The SoC subsystem 310 replaces redundant HDCs from the HDAs. The SoC subsystem 310 further controls which HDAs are activated or powered up. For example, the SoC subsystem 310 may power up only one HDA. In alternative implementations, the SoC subsystem 310 may power up more than one HDA, for example to actively read/write data from one HDA while another HDA finishes a background task before powering down. The use of the SoC subsystem 310 reduces the amount of components on the MB 300, which further reduces manufacturing costs as well as reduces heat and power consumption.

FIG. 4A shows a data storage tray 400. FIG. 4A depicts a top view of an MB 410, which is placed over a plurality of HDAs 450. Slots 412 in the MB 410 allow clearance for rails of the HDAs 450. An extended tab 420 allows for power and data connection ports. The extended tab 420 is about half the width of the MB 410, which allows panelization, which during manufacturing allows multiple copies of the MB 410 to be cut out of a single board. For example, if the main board 410 is rotated 180 degrees, it can be placed along another MB 410, with the extended tabs 420 fitting together before the individual MBs 410 being cut. In other implementations the width of the extended tab 420 may be more or less than the width of the MB 410. A motor driver 451 and a sensor 452 are located under the main board 410, at a location corresponding to the location for a motor driver and a sensor on a standalone DSD. An SoC subsystem, such as the SoC subsystem 310 in FIG. 3, and a mux subsystem, such as the mux subsystem 320, may be centrally located on the main board 410 (not visible in FIG. 4A), but in other implementations may be located elsewhere as needed. For example, the SoC and mux subsystems may be located closer to an edge for easier mounting of HDAs 450 or for shorter connections.

FIG. 4B shows another view of the data storage tray 400. The main board 410 and the plurality of HDAs 450 are mounted onto a tray 402. In this view, a connector 422 and a power connector 424 are visible. The connector 422 may be a mini SAS connector, although in other implementations, the connector 422 may be a connector for another suitable protocol. The power connector 424 may be a 12V power connection, although in other implementations, other suitable power connectors may be used.

Mounting the HDAs 450 directly to the MB 410, as in FIG. 4B, allows the use of existing HDA to board connectors and signal impedance matching techniques, which provides a simple, low cost implementation.

FIG. 4C depicts an alternate data storage tray 401. The data storage tray 401 differs from the data storage tray 400 in FIG. 4B in that the MB 410 includes a second extended tab 426. The second extended tab 426 is less than half the width of the main board 410, and is also less than the width of the extended tab 420, although in other implementations the width of the second extended tab 426 may vary as needed. The second extended tab 426 includes an interface 404. The interface 404 may be used for lights, such as status indicators or other light emitting diodes (LED), additional display, or another connection, such as a data connection.

FIG. 5A shows a conceptual diagram of a data storage tray 500. The data storage tray 500 includes a MB 550 including a SoC subsystem 530, a power converter 540, a fan controller 545, and a mux subsystem 520. The SoC subsystem 530 may include a processor as well as other circuitry incorporated into a single chip. The data storage tray 500 further includes a plurality of HDAs 501, each of which includes a bridge board 510. Unlike in FIGS. 4A-C, the HDAs 501 are not directly mounted or attached to the MB 550, but use bridge boards 510. The use of the bridge boards 510 allows easier hot plug and replacement. The HDA 501 can be removed while leaving the bridge board 510 connected to the main board 550, because the connectors, such as the HDA connector 240, facilitate removal of the HDA 501. Alternatively, the bridge board 510 may be removed along with the HDA 501 such that another HDA 501, which may or may not have a respective bridge board 510, may be connected to the MB 550. The use of the bridge boards 510 allows further flexibility in the types of connections and connectors compatible with the MB 550.

FIG. 5B depicts a simplified diagram of the data storage tray 500. The MB 550 includes regulators 552, a power input 542, a RAM 532, the SoC subsystem 530, a data connection 554, and a fan out bridge 556. The data connection 554 may be an SAS interface for connecting to a compute node, but in alternative implementations other suitable protocols may be used. Motor controllers, such as the motor controller 212, on the bridge board 510 allows the HDAs 501 to be hot swapped with emergency power off retract ability, which safely prevents heads, such as the head assembly 230, from contacting and damaging the disks, such as the platter 220.

FIGS. 6 and 7 depict implementations configured for distributed computing. FIG. 6 shows a diagram of a data storage tray 600, which includes rack connectors 640, a compute node 645, a power converter 650, a fan and cabinet services 660, an SoC subsystem 610, a mux subsystem 620, and an HDA bank 630. The SoC subsystem 610 includes a clock 619, regulators 615, a RAM 613, a flash memory 617, and an SoC 611. The SoC 611 may include a processor as well as other circuitry integrated into a single chip. The mux subsystem 620 includes a preamp mux 622 and a mux controller 624. The HDA bank 630 includes a plurality of HDAs 632, and a respective plurality of sensors 634. The rack connectors 640 include a power connection and an external data connection (or network connection), which connects to the compute node 645. The compute node 645 may be a processor for use in a distributed computing system, and may be aware of other compute nodes to share data object manipulation and perform distributed computing tasks, such as running a SQL database. Although Ethernet is a common network interface, other suitable protocols may be used for the external data/network connection. Likewise, the host interface may be SAS, although PCIe or other protocols may be used.

FIG. 7 presents a diagram of another implementation configured for distributed computing. A data storage tray 700 includes an HDA bank 730, and an MB 701 which further includes a power converter 750, a fan and cabinet services 760, an SoC subsystem 710, and a mux subsystem 720. The SoC subsystem 710 includes a clock 719, a flash memory 717, an SoC 711, a RAM 713, and regulators 715. The SoC 711 may include a processor as well as other circuitry integrated into a single chip. The mux subsystem 720 includes a preamp mux 722 and a mux controller 724. The HDA bank 730 includes a plurality of HDAs 732, with a corresponding plurality of sensors 734.

Unlike the data storage tray 600, the data storage tray 700 lacks a compute node and rack connectors. An external data connection or network connection 740, such as Ethernet or other suitable protocol, allows direct connection to the SoC subsystem 710 for a distributed computing system to share data object manipulation and distributed computing tasks with at least one external processor.

Those of ordinary skill in the art will appreciate that the various illustrative logical blocks, modules, and processes described in connection with the examples disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. Furthermore, the foregoing processes can be embodied on a computer readable medium which causes a processor or computer to perform or execute certain functions.

To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, and modules have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Those of ordinary skill in the art may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

The various illustrative logical blocks, units, modules, and controllers described in connection with the examples disclosed herein may be implemented or performed with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

The activities of a method or process described in connection with the examples disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. The steps of the method or algorithm may also be performed in an alternate order from those provided in the examples. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable media, an optical media, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an Application Specific Integrated Circuit (ASIC).

The foregoing description of the disclosed example implementations is provided to enable any person of ordinary skill in the art to make or use the implementations in the present disclosure. Various modifications to these examples will be readily apparent to those of ordinary skill in the art, and the principles disclosed herein may be applied to other examples without departing from the spirit or scope of the present disclosure. The described implementations are to be considered in all respects only as illustrative and not restrictive and the scope of the disclosure is, therefore, indicated by the following claims rather than by the foregoing description. All changes which come within the meaning and range of equivalency of the claims are to be embraced within their scope.