190348 ⎘
Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units; Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA , cycle steal Multiplexed DMA
METHOD AND APPARATUS FOR HARDWARE RESOURCE SHARING IN A DIRECT MEMORY ACCESS CONTROLLER
#2CONFIGURABLE MEMORY DEVICE
#3LOW POWER 4:1 MULTIPLEXED RANK DUAL INLINE MEMORY MODULES
#4DYNAMIC RANDOM ACCESS MEMORY (DRAM) COMPONENT FOR HIGH-PERFORMANCE, HIGH-CAPACITY REGISTERED MEMORY MODULES
#5High Speed Data Packet Flow Processing with Offload
#6MICRO-CONTROLLER CHIP CONTAINING MULTI-PROTOCOL COMMUNICATION INTERFACE PERIPHERAL AND OPERATION METHOD THEREOF
#7FFT ENGINE HAVING COMBINED BIT-REVERSAL AND MEMORY TRANSPOSE OPERATIONS
#8Peer-To-Peer Communication Using Drain Buffers In Multi-Function Device
#9ADAPTIVE INTERFACE STORAGE DEVICE
#10LINK LAYER-PHY INTERFACE ADAPTER
#11COMPUTATIONAL MEMORY
#12DYNAMIC RANDOM ACCESS MEMORY (DRAM) COMPONENT FOR HIGH-PERFORMANCE, HIGH-CAPACITY REGISTERED MEMORY MODULES
#13High Speed Data Packet Flow Processing with Offload
#14Hardware-based security authentication
#15REMOTELY-POWERED SENSING SYSTEM WITH MULTIPLE SENSING DEVICES
#16Computational memory
#17Adaptive interface storage device with multiple storage protocols including solid state drive storage devices
#18FFT ENGINE HAVING COMBINED BIT-REVERSAL AND MEMORY TRANSPOSE OPERATIONS
#19Frame scheduling based on an estimated direct memory access (DMA) latency and apparatus for time aware frame scheduling
#20COMPUTATIONAL MEMORY
#21Hardware-based security authentication
#22SECURE MASTER AND SECURE GUEST ENDPOINT SECURITY FIREWALL
#23REDUCING LATENCY FOR MEMORY OPERATIONS IN A MEMORY CONTROLLER
#24Information processing system, information processing method, and information processing device to reduce load on an information processing unit
#25Network interface device with bus segment width matching
#26Data transmission system and operation method thereof
#27Digital signal processing circuit and corresponding method of operation
#28Dynamic random access memory (DRAM) component for high-performance, high-capacity registered memory modules
#29High speed data packet flow processing
#30Communication control device, communication control method, information processing device, information processing method, and computer program product
#31Hardware-based security authentication
#32Systems and methods for single-wire in-band pulse-addressable multiplexer
#33Reducing latency for memory operations in a memory controller
#34Narrow DRAM channel systems and methods
#35Digital signal processing circuit and corresponding method of operation
#36MEMORY DEVICE AND ASSOCIATED FLASH MEMORY CONTROLLER
#37FFT engine having combined bit-reversal and memory transpose operations
#38Efficient storage architecture for high speed packet capture
#39Configuring first subsystem with a master processor and a second subsystem with a slave processor
#40High-speed replay of captured data packets
#41Dynamic random access memory (DRAM) component for high-performance, high-capacity registered memory modules
#42Adaptive interface storage device with multiple storage protocols including NVMe and NVMe over fabrics storage devices
#43Communication system and operation method
#44Remotely-powered sensing system with multiple sensing devices
#45High-speed data packet capture and storage with playback capabilities
#46Synchronous dynamic random access memory (SDRAM) dual in-line memory module (DIMM) having increased per data pin bandwidth
#47Microcontroller with configurable logic peripheral
#48Link layer-PHY interface adapter
#49Computational memory
#50Programmable arbitrary sequence direct memory access controller for configuring multiple core independent peripherals
#51High speed data packet flow processing
#52Intelligent SAS phy connection management
#53FFT engine having combined bit-reversal and memory transpose operations
#54Systems and methods for providing multiple memory channels with one set of shared address pins on the physical interface
#55System and method for individual addressing
#56High-speed replay of captured data packets
#57Adaptive interface storage device with multiple storage protocols including NVME and NVME over fabrics storage devices
#58Efficient storage architecture for high speed packet capture
#59High-speed data packet capture and storage with playback capabilities
#60Intelligent SAS phy connection management
#61Remotely powered, multisite sensing system with a shared, two-wire bus for power and communication
#62Adaptive interface storage device with multiple storage protocols including NVME and NVME over fabrics storage devices
#63Accessing status information
#64Dynamic random access memory (DRAM) component for high-performance, high-capacity registered memory modules
#65System and method for individual addressing
#66Circuitry to alleviate printed circuit board routing congestion
#67FULL-DUPLEX MEMORY ACCESS SYSTEMS AND METHODS FOR IMPROVED QUALITY OF SERVICE (QOS)
#68System and method for individual addressing
#69Efficient testing of direct memory address translation
#70Efficient testing of direct memory address translation
#71Secure master and secure guest endpoint security firewall
#72Remotely powered, multisite sensing system with a shared, two-wire bus for power and communication
#73Circuitry to alleviate printed circuit board routing congestion
#74Storage in multi-queue storage devices using queue multiplexing and access control
#75Apparatuses and methods for multilane universal serial bus (USB2) communication over embedded universal serial bus (eUSB2)
#76Synchronous transmission device and synchronous transmission method
#77Universal serial bus type C transmission line and transmission device
#78Remotely-powered sensing system with multiple sensing devices
#79READ WRITEABLE RANDOMLY ACCESSIBLE NON-VOLATILE MEMORY MODULES
#80Reconfigurable fabric direct memory access with multiple read or write elements
#81Methods and apparatus for aggregating packet transfer over a virtual bus interface
#82RECONFIGURABLE FABRIC ACCESSING EXTERNAL MEMORY
#83System and method for individual addressing
#84Detecting and sparing of optical PCIE cable channel attached IO drawer
#85Multicast apparatuses and methods for distributing data to multiple receivers in high-performance computing and cloud-based networks
#86Accessing status information
#87Ring bus architecture for use in a memory module
#88Memory controller with virtual controller mode
#89Dynamic random access memory (DRAM) component for high-performance, high-capacity registered memory modules
#90System, USB Type-C connector and method to transmit encoded data
#91Coupling connector to management port or system port
#92Remotely powered, multisite sensing system with a shared, two-wire bus for power and communication
#93System for switching between a single node PCIe mode and a multi-node PCIe mode
#94Memory module including plurality of memory packages with reduced power consumption
#95Secure routing of trusted software transactions in unsecure fabric
#96High density content addressable memory
#97Catalyst for treating exhaust gas
#98Data bus inversion (DBI) encoding based on the speed of operation
#99BUS-BIT-ORDER ASCERTAINMENT
#100High bandwidth low latency data exchange between processing elements
#101High bandwidth low latency data exchange between processing elements
#102Configurable serial and pulse width modulation interface
#103Parallel and serial data with controller, delay, and register circuits
#104Transceiver multiplexing over USB type-C interconnects
#105Ring bus architecture for use in a memory module
#106Low overhead hierarchical connectivity of cache coherent agents to a coherent fabric
#107Optical interconnect in high-speed memory systems
#108Cost-effective device interface for data input and output
#109Data transmission using PCIe protocol via USB port
#110Power delivery and data transmission using PCIe protocol via USB type-C port
#111Multicore, multibank, fully concurrent coherence controller
#112Detecting and sparing of optical PCIE cable channel attached IO drawer
#113Detecting and sparing of optical PCIE cable channel attached IO drawer
#114Peripheral register parameter refreshing
#115Read writeable randomly accessible non-volatile memory modules
#116COMMON DIE IMPLEMENTATION FOR MEMORY DEVICES
#117File system extension system and method
#118Methods and apparatus for aggregating packet transfer over a virtual bus interface
#119MULTI-CHANNEL AUDIO COMMUNICATION IN A SERIAL LOW-POWER INTER-CHIP MEDIA BUS (SLIMBUS) SYSTEM
#120Multi-processor, multi-domain, multi-protocol cache coherent speculation aware shared memory controller and interconnect
#121Resource allocation by virtual channel management and bus multiplexing
#122Universal serializer architecture
#123Time multiplexing at different rates to access different memory types
#124Multi-petascale highly efficient parallel supercomputer
#125IR enabled gating of TAP and WSP shift, capture, transfer
#126Time-constrained data copying between storage media
#127Storage module and method for determining ready/busy status of a plurality of memory dies
#128Device and method to assign device pin functionality for multi-processor core devices
#129Device and method to assign device pin ownership for multi-processor core devices
#130Common public radio interface (CPRI) lane controller coupled to direct memory access (DMA) wherein a time division duplex (TDD) steers control of CPRI
#131Memory system, memory interfacing device, and interfacing method performed in the memory system
#132Stacked memory device control
#133Segmenting bus topology
#134Stacked memory device control
#135Fast exit from low-power state for bus protocol compatible device
#136Serial bus interface to enable high-performance and energy-efficient data logging
#137Real-time data acquisition using chained direct memory access (DMA) channels
#138Remote transactional memory
#139Catalyst for treating exhaust gas
#140Accessing remote storage devices using a local bus protocol
#141Software Enabled Network Storage Accelerator (SENSA) - network - disk DMA (NDDMA)
#142ELECTRONIC DEVICE, SYNTHESIZED STREAM TRANSMITTING METHOD, AND PROGRAM
#143Electronic device and semiconductor device
#144Functional node for an information transmission network and corresponding network
#145Data storage raid architecture system and method
#146Programmable interrupt routing in multiprocessor devices
#147Remotely powered, multisite sensing system with a shared, two-wire bus for power and communication
#148Method and apparatus for mouse with integrated mass memory
#149Systems and methods for automatic root port to non-transparent bridge switching for a PCI express interconnect architecture
#150Transactional memory that performs an ALUT 32-bit lookup operation
#151Resource allocation by virtual channel management and bus multiplexing
#152Methods for sharing bandwidth across a packetized bus and systems thereof
#153Data storage apparatus
#154Control circuitry module group, electric device and modem device
#155Intelligent connector and bus controller
#156Data bus host and controller switch
#157Memory transaction ordering
#158Memory including a band width conversion unit, memory system and memory control method using the same
#159System and method for providing PCIE over displayport
#160MULTIPLEXER FOR SIGNALS ACCORDING TO DIFFERENT PROTOCOLS
#161System and method for direct memory access transfers
#162SIGNAL PROCESSING APPARATUS
#163Control device and image forming apparatus with two controllers
#164Method for providing a generic interface and microcontroller having a generic interface
#165Data storage controller with multiple pipelines
#166MOTHERBOARD WITH PERIPHERAL COMPONENT INTERCONNECT EXPRESS SLOTS
#167System and method for a bus interface
#168Programmable peripheral interconnect
#169Incoming bus traffic storage system
#170Data bus inversion (DBI) encoding based on the speed of operation
#171Adaptable datapath for a digital processing system
#172Flexible and expandable memory architectures
#173Scalable storage system having multiple storage channels
#174Secure master and secure guest endpoint security firewall
#175Transactional memory that performs an ALUT 32-bit lookup operation
#176Multi-master cache coherent speculation aware memory controller with advanced arbitration, virtualization and EDC
#177Deadlock-avoiding coherent system on chip interconnect
#178Fast exit from low-power state for bus protocol compatible device
#179Transactional memory that performs an atomic metering command
#180System and method for a bus interface
#181Incoming bus traffic storage system
#182Data source, destination and input/output circuit with multiplexer and flip-flop
#183Time multiplexing at different rates to access different memory types
#184Data register control from TAP+ATC or discrete WSP signals
#185TAP with serial I/O coupled to TCK
#186System and method for providing PCIE over displayport
#187Optical interconnect in high-speed memory systems
#188Multi-petascale highly efficient parallel supercomputer
#189Adaptable datapath for a digital processing system
#190Gates and sync circuitry connecting TAP to serial communications circuitry
#191Segmenting bus topology
#192IEEE 1149.1 and P1500 test interfaces combined circuits and processes
#193IEEE 1149.1 and P1500 test interfaces combined circuits and processes
#194Serial I/O using JTAG TCK and TMS signals
#195Flexible and expandable memory architectures
#196IEEE 1149.1 and P1500 test interfaces combined circuits and processes
#197Adaptable datapath for a digital processing system
#198IEEE 1149.1 and P1500 test interfaces combined circuits and processes
#199Serial I/O using JTAG TCK and TMS signals
#200System and method for providing PCIe over displayport
#201Adaptable datapath for a digital processing system
#202Cache for instruction set architecture using indexes to achieve compression
#203Serial data I/O on JTAG TCK with TMS clocking
#204System and method for in situ debug
#205Scalable tweak engines and prefetched tweak values for encyrption engines
#206Bit-mapped DMA transfer with dependency table configured to monitor channel between DMA and array of bits to indicate a completion of DMA transfer
#207Bit-mapped DMA transfer with dependency table configured to monitor status so that a processor is not rendered as a bottleneck in a system
#208Auto-zeroing receiver for memory interface devices
#209Methods and systems for generating interrupts by a response direct memory access module
#210Efficient testing of direct memory address translation
#211Fast reconfiguration of the data plane of a hardware forwarding element
#212Efficient testing of direct memory address translation
#213High-speed data packet capture and storage with playback capabilities
#214Bit-mapped DMA transfer with dependency table configured to monitor status so that a processor is not rendered as a bottleneck in a system
#215Solid state drive multiplexer
#216Method and apparatus for memory access
#217Transactional memory that performs an atomic metering command
#218Bit-mapped DMA transfer with dependency table configured to monitor status so that a processor is not rendered as a bottleneck in a system
#219Offload pipeline for data mirroring
#220Data storage assembly for archive cold storage
#221Configurable storage blocks with embedded first-in first-out and delay line circuitry
#222Methods and apparatus for rapid interrupt lookups
#223Backup from network attached storage to sequential access media in network data management protocol environments