Method and apparatus for improving power gain and loss for interconect configurations

Description

RELATED APPLICATIONS

This is a non provisional application of a provisional application Ser. No. 61/215,369 by James V. Russell filed May 4, 2009

BACKGROUND

1. Field

In attaching an electrical component to the bottom side and/or the top side of a printed circuit board (PCB), there is the problem of power loss or due to the distance of the capacitance to the points on a corresponding integrated circuit (IC) for which it is intended. It is not possible to physically locate the capacitance directly to the contact pads on the printed circuit which correspond to the input output points of an integrated circuit or in the case of a test board the corresponding points of the test socket. Similarly there is the problem of inadequate dissipation due to the distance of a resistance to the electrical component. Again, it is not very likely to physically locate the resistance at the contact pads on the printed circuit board.

It would therefore be desirable to have a method and apparatus that provides for close proximate placement of the capacitance or of the resistance which shall be referred to as a power modification component since it either better dissipates power (power loss) (resistance) or better distributes power (power gain) (capacitance) to the IC or other electrical component on a PCB to provide better power gain or distribution or power loss or dissipation.

SUMMARY

The present disclosure provides for attaching and embedding a capacitance or a resistance directly to the bottom side of pads that are located to extend over and beyond the vias of the PCB so that a portion of the pad containing the embedded power modification component (capacitance or resistance) is located beyond where the visa are located. Each of the pads will be connected to the endpoints of the power modification component located underneath it through an opening in the dielectric material under the pads to permit conduction through the opening. In this way the capacitance and the resistance will have a closer contact point with the electrical component.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a an illustration of standard interconnect configuration showing placement of a capacitance or resistance;

FIG. 2 A is illustrates the interconnect configuration with placement of the capacitance or resistance in accordance with the present disclosure;

FIG. 2B is another embodiment of the present disclosure showing the vias aligned vertically one on top of another for a finer pitch;

FIG. 3 is another embodiment of the present disclosure in which the embedded component is a component aligned vertically within the board; and

FIG. 4 is an embodiment of the present disclosure showing an embedded resistance and an embedded capacitance within the board aligned vertically and horizontally.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT(S)

Referring now to the drawings, FIG. 1 illustrates the typical interconnect configuration where the capacitance or resistance is placed a considerable distance away from the electrical test structure housing of an IC chip (not shown). FIG. 2 illustrates the interconnect configuration of the present disclosure. In this configuration, the power modification component 5 which can be, but is not limited to, either the capacitance 5c (FIG. 4) or the resistance 5a (FIG. 3) is embedded under pads 7 within the footprint of the electrical test structure housing of an IC chip (not shown). The pads 7 are located with the embedded portion not covering the vias or blinds 11 but placed in proximity of the electrical component. In this way the placement can provide for better power distribution by being close to the electrical component so that there is little power dissipation and the capacitance does not become inductive. Similarly by the same close proximity of the resistance to the electrical component power dissipation is provided when required. Distant placement of the resistance from the electrical component results in a reduction of the power dissipation, a problem addressed and resolved by the present disclosure as shown in FIG. 3 of the drawings.

FIG. 2A illustrates an embodiment of the present disclosure showing an interconnect configuration in which a power modification component 5 e.g. resistance 5a (FIG. 3) or capacitance 5c (FIG. 4) is attached to the bottom sides of the pads 7 formed by preferably a copper layer of a printed circuit board (PCB). The embedded power modification component 5 (such as but not limited to a capacitance or resistance) is located below a layer of copper foil followed by dielectric layer. The power modification component 5 is surrounded on its sides by Prepreg material e.g. fiber reinforced or unreinforced epoxy or plastic material. The power modification component 5 is attached to the pads 7 layer by solder paste, conductive epoxy, or metallic plating 14. It is understood that any other known means of attachment can be used as well and that the present disclosure also is not limited to the particular materials of copper foil, dielectric layer and Prepreg material described herein. As shown in FIG. 2A the power modification component 5 is embedded so as to be near but not block the vias or blinds 11 for the PCB 8. Preferably the capacitance 5c will be a 0201 cap. However any desired capacitance value or size that can be accommodated can be used. As seen in FIG. 4, the capacitance 5c is attached by a conductive epoxy, solder paste, or metallic plating 14.

FIG. 3 shows another embodiment of improved power dissipation by embedding a resistor 5a in a pc board 8. An opening is created beneath the pad 7a at the top of the interposer board and the pad 7b at the bottom of the pc board 10 and a resistor 5a is vertically positioned within the opening in-between the top and bottom pads 7a and 7b, respectively, and in effect acts as a via for the effected layers of the pc board 10, which it is assumed can be a multilayer pc board, so that the electrical connection is through the resistance 5a embedded in the pc board 10. The pads 7a and 7b, respectively, are connected to the resistance 5a. Openings between the ends points of the resistance 5a and the pads 7a and 7b, respectively, in the pc board 8 can be filled with solder, metallic plating or conductive epoxy 14.

FIG. 4 shows another embodiment of the present disclosure with an embedded capacitance 5c and the embedded resistance 5a of FIG. 3 together in the same pc board 8.

While certain embodiments have been shown and described, it is distinctly understood that the present disclosure is not limited thereto but may be otherwise embodied within the scope of the appended claims.