Controlled area solder bonding for dies
US20130241051A1
2013-09-19
13/419,779
2012-03-14
✅ Patent granted
US 8,531,040 B1
2013-09-10
-
-
David Zarneke
Fogg & Powers LLC
2032-03-14
Abstract:
A method of fabricating a semiconductor comprises forming a plurality of stud bumps in a pattern having a geometrical shape on a surface of a substrate, the pattern defining a periphery of a bonding area on the surface of the substrate, and placing a solder material in the bonding area such that the solder material is surrounded by the stud bumps. The solder material is heated to a temperature where the solder material begins to flow within the bonding area. A bonding surface of a die is pressed onto the stud bumps with a sufficient pressure to crush the stud bumps a predetermined extent such that the solder material substantially evenly spreads between the stud bumps within the bonding area. The solder material is then solidified to form a final solder area that conforms to the geometrical shape of the pattern of stud bumps.
Assignee:
- HONEYWELL INTERNATIONAL INC. 10,240 🇺🇸 Morristown, NJ, United States
Applicant:
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Classification:
H01L2924/01322 » CPC further
Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by; Alloys; Binary Alloys Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
H01L24/83 » CPC main
Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto; Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
B81B7/0048 » CPC further
Microstructural systems; Auxiliary parts of microstructural devices or systems; Packages or encapsulation for reducing stress inside of the package structure between the MEMS die and the substrate
B81C1/00095 » CPC further
Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems without movable or flexible elements Interconnects
H01L24/29 » CPC further
Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto; Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto; Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto; Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
H01L24/32 » CPC further
Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto; Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto; Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto; Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
H01L2224/27013 » CPC further
Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by; Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto; Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto; Manufacturing methods; Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
H01L2224/73103 » CPC further
Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by; Means for bonding being of different types provided for in two or more of groups; Location prior to the connecting process on the same surface Bump and layer connectors
H01L2224/81192 » CPC further
Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by; Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector; Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
H01L2224/81903 » CPC further
Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by; Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector with the bump connector not providing any mechanical bonding; Pressing the bump connector against the bonding areas by means of another connector by means of a layer connector
H01L2224/83136 » CPC further
Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by; Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector; Aligning involving guiding structures, e.g. spacers or supporting members
H01L2224/83801 » CPC further
Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by; Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector; Bonding techniques Soldering or alloying
H01L2224/26175 » CPC further
Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by; Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto; Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto; Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body Flow barriers
H01L2224/83101 » CPC further
Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by; Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
H01L2224/73204 » CPC further
Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by; Means for bonding being of different types provided for in two or more of groups; Location after the connecting process on the same surface; Bump and layer connectors the bump connector being embedded into the layer connector
H01L2224/83192 » CPC further
Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by; Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector; Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
H01L2224/92125 » CPC further
Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by; Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups - ; Specific sequence of method steps; Connecting a surface with connectors of different types; Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
H01S5/0237 » CPC further
Semiconductor lasers; Structural details or components not essential to laser action; Mountings; Housings; Method for mounting laser chips; Fixing laser chips on mounts by soldering
H01L2924/0105 » CPC further
Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by; Chemical elements Tin [Sn]
H01L2924/01014 » CPC further
Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by; Chemical elements Silicon [Si]
H01L2924/01032 » CPC further
Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by; Chemical elements Germanium [Ge]
H01L2924/01079 » CPC further
Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by; Chemical elements Gold [Au]
H01L2924/10253 » CPC further
Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by; Details of semiconductor or other solid state devices to be connected; Material of the semiconductor or solid state bodies; Semiconducting materials; Elemental semiconductors, i.e. Group IV Silicon [Si]
H01L2924/1461 » CPC further
Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by; Details of semiconductor or other solid state devices to be connected; Mixed devices MEMS
H01L2924/12042 » CPC further
Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by; Details of semiconductor or other solid state devices to be connected; Device type; Passive devices, e.g. 2 terminal devices; Optical Diode LASER
H01L2924/00 » CPC further
Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by
H01L23/498 IPC
Details of semiconductor or other solid state devices; Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered constructions Leads, on insulating substrates,
H01L21/603 IPC
Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof; Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer; Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups - , e.g. sealing of a cap to a base of a container; Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving the application of pressure, e.g. thermo-compression bonding
H01L23/48 IPC
Details of semiconductor or other solid state devices Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
H01L23/52 IPC
Details of semiconductor or other solid state devices Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
H01L29/40 IPC
Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor Electrodes ; Multistep manufacturing processes therefor
H01L21/44 IPC
Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof; Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups, , , and with or without impurities, e.g. doping materials Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups -
Description
BACKGROUND
Controlling the area where solder flows and limiting the bonding area during die attach is very difficult. Generally, the entire die is bonded, which results in excessive stress to the die. This can be very detrimental to the performance of a die such as a micro-electro-mechanical systems (MEMS) sensor.
In general, a small solder area is all that is required to meet strength requirements for die attach. High temperature solders are usually extremely strong, and have the desirable attribute of high material elasticity, which is critical to the predictable performance of MEMS sensors. When using solders for die attach, it can be difficult to control the final area, shape, and location of the solder joint.
The most common solution for attaching die is to use a sufficient volume of solder to completely cover the back side of the die, and to overflow next to the die. While this approach can make for a solid joint, it also imparts great stress on the attached die because of the mismatch of the coefficient of thermal expansion (CTE) of the materials used, including the die material, the substrate or package to which the die is mounted, and the solder itself. For example, silicon die have a CTE in the range of about 2 to 3 ppm/° C. Ceramics to which die are often mounted, such as alumina, have a higher CTE, typically around 7 ppm/° C., and printed circuit boards have a much higher CTE.
Die stress can be reduced greatly by controlling the area over which a die is soldered. A small area near the center is usually best, but this can depend on the design and purpose of the die, especially when dealing with MEMS sensors. Unfortunately, die solders are notoriously difficult to control as the solders wet unpredictably, and voiding and flow are hard to predict. Simply placing a small amount of solder near the center of a die and reflowing can result in almost any shape and thickness of final solder area, even when conditions are carefully controlled. Other methods of die attach such as pure gold stud bump (GSB) thermocompression can control the bond area, but suffer from the soft, inelastic nature of the stud bump material.
SUMMARY
A method of fabricating a semiconductor comprises forming a plurality of stud bumps in a pattern having a geometrical shape on a surface of a substrate, the pattern defining a periphery of a bonding area on the surface of the substrate, and placing a solder material in the bonding area such that the solder material is surrounded by the stud bumps. The solder material is heated to a temperature where the solder material begins to flow within the bonding area. A bonding surface of a die is pressed onto the stud bumps with a sufficient pressure to crush the stud bumps a predetermined extent such that the solder material substantially evenly spreads between the stud bumps within the bonding area. The solder material is then solidified to form a final solder area that conforms to the geometrical shape of the pattern of stud bumps.
DRAWINGS
Understanding that the drawings depict only exemplary embodiments and are not therefore to be considered limiting in scope, the exemplary embodiments will be described with additional specificity and detail through the use of the accompanying drawings, in which:
FIGS. 1A-1D are side views of a die attach process used in fabricating a semiconductor device according to one embodiment;
FIGS. 2A-2D are top views of the die attach process of FIGS. 1A-1D;
FIGS. 3A-3D are side views of a die attach process used in fabricating a semiconductor device according to another embodiment;
FIGS. 4A-4D are top views of the die attach process of FIGS. 3A-3D;
FIGS. 5A-5D are side views of a die attach process used in fabricating a semiconductor device according to a further embodiment;
FIGS. 6A-6D are top views of the die attach process of FIGS. 5A-5D;
FIGS. 7A-7D are side views of a die attach process used in fabricating a semiconductor device according to an alternative embodiment; and
FIGS. 8A-8D are top views of the die attach process of FIGS. 7A-7D.
In accordance with common practice, the various described features are not drawn to scale but are drawn to emphasize specific features relevant to the exemplary embodiments.
DETAILED DESCRIPTION
In the following detailed description, embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It is to be understood that other embodiments may be utilized without departing from the scope of the invention. The following detailed description is, therefore, not to be taken in a limiting sense.
A method is provided for controlling the solder bond area during die attachment to a substrate in fabricating a semiconductor device. The present method produces a controlled area solder bond on the surface of the die when attached to a substrate during packaging. The present die attach process provides more stable stress on the die such as a micro-electro-mechanical systems (MEMS) die, and thus more stable performance over temperature.
In the present technique, a plurality of stud bumps are formed in a predetermined pattern on a surface of a substrate, with the pattern defining a periphery of a bonding area on the surface of the substrate. The stud bumps form a “picket fence” around the periphery of the bonding area on the substrate. A solder material is then placed in the bonding area such that it is surrounded by the stud bumps. In exemplary embodiments, the solder material can be in the form of a small solid “preform” such as a solder sphere, or small solder particles suspended in a paste.
The solder material is heated to a temperature such that it begins to flow within the bonding area. A bonding surface of a die is then pressed onto the stud bumps with a sufficient pressure to crush the stud bumps such that the solder substantially evenly spreads between the stud bumps within the bonding area. The solder material is solidified to form a final solder area that conforms to the shape of the predetermined pattern of stud bumps.
The use of a “picket fence” of stud bumps placed near the desired edge of the solder area does not necessarily form a dam for the solder, but gives the solder something to wet to. The surface tension of the molten solder as it wets the stud bumps makes the solder cling to the stud bumps and defines the final solder area. The stud bumps can also be used to control the bondline thickness of the solder, since the stud bumps resist force in a predictable fashion. Applying a certain force to the die will crush the stud bumps to a predictable extent while spreading the solder to the stud bumps. If the pattern of stud bumps and forces used to create the bond are carefully chosen, a joint with the strength and elasticity of the high temperature solder can be formed with controlled location and size.
In a semiconductor device fabricated according to the present technique, the die is attached to the substrate at a controlled solder bond area that includes the solder material that is substantially evenly spread between the stud bumps coupled between the substrate and the die. The stud bumps are coupled in a pattern having a geometrical shape and define a periphery of the solder bond area. The solder material conforms to the geometrical shape of the pattern of the stud bumps.
Additional details of the present approach are described as follows with reference to the drawings.
FIGS. 1A-1D and 2A-2D illustrate a die attach process according to one embodiment. Initially, a plurality of stud bumps 110 are formed in a predetermined pattern having a geometrical shape around the edge of a desired bonding area 114 on a surface of a die attach substrate 118. As shown in FIG. 2A, stud bumps 110 are formed in a circular pattern to form a “picket fence” on the surface of substrate 118, although other geometric patterns may be utilized as described hereafter.
The stud bumps 110 can be formed on bonding area 114 by conventional techniques such as formation by a ball (wire) bonder. The stud bumps 110 can be composed of various metals such as gold, platinum, copper, combinations thereof, or the like.
The substrate 118 can include, for example, a ceramic material such as alumina (aluminum oxide), aluminum nitride, silicon nitride, silicon, glasses; plated metals such as nickel alloys, including Kovar™ alloy (iron-nickel-cobalt), Alloy 42 (nickel-iron alloy), or the like; or a printed circuit board (PCB).
A solder material in the form of a spherical solder preform 120, is then placed in bonding area 114 such that solder preform 120 is surrounded by stud bumps 110, as illustrated in FIGS. 1B and 2B. The solder preform 120 is heated to the solder melting temperature so that it begins to lose its shape and flow within bonding area 114, as shown in FIGS. 1C and 2C. The solder material can include, for example, eutectic alloys such as AuSn, AuSi, or AuGe, Indium alloys, or the like.
A die 130 is then pressed onto stud bumps 110 as depicted in FIG. 1D. The die 130 can include, for example, a MEMS sensor, a laser diode, an inertial sensor, or the like. Applying a certain force (such as a few newtons) to die 130 crushes stud bumps 110 a predictable extent while spreading the solder material to stud bumps 110. The surface tension of the solder material makes it cling to stud bumps 110 as the solder material wets stud bumps 110 while spreading. This defines a final solder area 132 in which the solder material is evenly spread between stud bumps 110. In this embodiment, the solder material conforms to the circular pattern of stud bumps 110 to form a circular solder bond 134, as depicted in FIG. 2D.
FIGS. 3A-3D and 4A-4D illustrate a die attach process according to another embodiment. Initially, a plurality of stud bumps 210 are formed in a predetermined pattern around the edge of a desired bonding area 214 on a surface of a die attach substrate 218. As shown in FIG. 4A, stud bumps 210 are formed in a circular pattern on the surface of substrate 218. The stud bumps 210 can be formed on bonding area 214 by conventional deposition techniques, and can be composed of various metals as described previously.
A solder material in the form of a rectangular solder preform 220, is then placed in bonding area 214 such that solder preform 220 is surrounded by stud bumps 210, as illustrated in FIGS. 3B and 4B. The solder preform 220 is then heated to the solder melting temperature so that it begins to lose its shape and flow within bonding area 214, as shown in FIGS. 3C and 4C.
A die 230, such as a MEMS sensor die, is then pressed onto stud bumps 210 as depicted in FIG. 3D. Applying a certain force to die 230 crushes stud bumps 210 while spreading the solder material towards stud bumps 210. The surface tension of solder material 220 makes it cling to stud bumps 210 as the solder material wets stud bumps 210 while spreading. This defines a final solder area 232 in which the solder material is evenly spread between stud bumps 210. In this embodiment, the solder material conforms to the circular pattern of stud bumps 210 to form a circular solder bond 234, as depicted in FIG. 4D.
FIGS. 5A-5D and 6A-6D illustrate a die attach process according to a further embodiment. A plurality of stud bumps 310 are formed in a predetermined pattern around the edge of a desired bonding area 314 on a surface of a die attach substrate 318. As shown in FIG. 6A, stud bumps 310 are formed in a circular pattern on the surface of substrate 318. The stud bumps 310 can be formed on bonding area 314 by conventional deposition techniques, and can be composed of various metals as described previously.
A solder preform 320 such as a cylindrical preform is located in bonding area 314 such it is surrounded by stud bumps 310, as illustrated in FIGS. 5B and 6B. The solder preform 320 is then heated to the solder melting temperature so that it begins to lose its shape and flow within bonding area 314, as shown in FIGS. 5C and 6C.
A die 330, such as a MEMS sensor die, is then pressed onto stud bumps 310 as depicted in FIG. 5D. Applying a certain force to die 330 crushes stud bumps 310 while spreading the solder material towards stud bumps 310. The surface tension of the solder material allows it to cling to stud bumps 310 as the solder material wets stud bumps 310. This defines a final solder area 332 in which the solder material is evenly spread between stud bumps 310. In this embodiment, the solder material conforms to the circular pattern of stud bumps 310 to form a circular solder bond 334, as depicted in FIG. 6D.
FIGS. 7A-7D and 8A-8D illustrate a die attach process according to an alternative embodiment. Initially, a plurality of stud bumps 410 are formed in a predetermined pattern around the edge of a desired bonding area 414 on a surface of a die attach substrate 418. As shown in FIG. 8A, stud bumps 410 are formed in a square or rectangular pattern on the surface of substrate 418. The stud bumps 410 can be formed on bonding area 414 by conventional deposition techniques, and can be composed of various metals as described previously.
A solder preform 420 such as a cylindrical preform is then placed in bonding area 414 such that it is surrounded by stud bumps 410, as illustrated in FIGS. 8A and 8B. The preform 420 is then heated to the solder melting temperature so that it begins to lose its shape and flow within bonding area 414, as shown in FIGS. 7C and 8C.
A die 430 such as a MEMS sensor die is then pressed onto stud bumps 410 as depicted in FIG. 7D. Applying a force to die 430 crushes stud bumps 410 while spreading solder material towards stud bumps 410. The surface tension of the solder material makes it cling to stud bumps 410 as the solder material wets stud bumps 410. This defines a final solder area 432 in which the solder material is evenly spread between stud bumps 410. In this embodiment, the solder material conforms to the square or rectangular shape of the pattern of stud bumps 410 to form a square or rectangular solder bond 434, as depicted in FIG. 8D.
Example Embodiments
Example 1 includes a method of fabricating a semiconductor device, comprising forming a plurality of stud bumps in a pattern having a geometrical shape on a surface of a substrate, the pattern defining a periphery of a bonding area on the surface of the substrate; placing a solder material in the bonding area such that the solder material is surrounded by the stud bumps; heating the solder material to a temperature where the solder material begins to flow within the bonding area; pressing a bonding surface of a die onto the stud bumps with a sufficient pressure to crush the stud bumps a predetermined extent such that the solder material substantially evenly spreads between the stud bumps within the bonding area; and solidifying the solder material to form a final solder area that conforms to the geometrical shape of the pattern of stud bumps.
Example 2 includes the method of Example 1, wherein the stud bumps are formed in a circular pattern on the surface of substrate.
Example 3 includes the method of Example 1, wherein the stud bumps are formed in a rectangular pattern on the surface of substrate.
Example 4 includes the method of any of Examples 1-3, wherein the stud bumps comprise gold, platinum, copper, or combinations thereof.
Example 5 includes the method of any of Examples 1-4, wherein the solder material is a spherical shaped preform.
Example 6 includes the method of any of Examples 1-4, wherein the solder material is a rectangular shaped preform.
Example 7 includes the method of any of Examples 1-4, wherein the solder material is a cylindrical shaped preform.
Example 8 includes the method of any of Examples 1-7, wherein the die comprises a micro-electro-mechanical systems (MEMS) sensor, an inertial sensor, or a laser diode.
Example 9 includes the method of any of Examples 1-8, wherein the substrate comprises a ceramic material, a plated metal, or a printed circuit board.
Example 10 includes the method of any of Examples 1-8, wherein the substrate comprises aluminum oxide, aluminum nitride, silicon nitride, silicon, or glass.
Example 11 includes a semiconductor device, comprising a substrate having an upper surface; a die attached to the substrate at a controlled solder bond area that includes a solder material that is substantially evenly spread between a plurality of stud bumps coupled between the substrate and the die; wherein the stud bumps are coupled in a pattern having a geometrical shape and define a periphery of the solder bond area; wherein the solder material conforms to the geometrical shape of the pattern of the stud bumps.
Example 12 includes the semiconductor device of Example 11, wherein the stud bumps are coupled in a circular pattern.
Example 13 includes the semiconductor device of Example 11, wherein the stud bumps are coupled in a rectangular pattern.
Example 14 includes the semiconductor device of any of Examples 11-13, wherein the stud bumps comprise gold, platinum, copper, or combinations thereof.
Example 15 includes the semiconductor device of any of Examples 11-14, wherein the die comprises a MEMS sensor.
Example 16 includes the semiconductor device of any of Examples 11-15, wherein the die comprises an inertial sensor.
Example 17 includes the semiconductor device of any of Examples 11-14, wherein the die comprises a laser diode.
Example 18 includes the semiconductor device of any of Examples 11-17, wherein the substrate comprises a ceramic material, or a plated metal.
Example 19 includes the semiconductor device of any of Examples 11-17, wherein the substrate comprises aluminum oxide, aluminum nitride, silicon nitride, silicon, or glass.
Example 20 includes the semiconductor device of any of Examples 11-17, wherein the substrate comprises a printed circuit board.
Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement, which is calculated to achieve the same purpose, may be substituted for the specific embodiments shown. Therefore, it is manifestly intended that this invention be limited only by the claims and the equivalents thereof.
Claims
What is claimed is:1. A method of fabricating a semiconductor device, comprising:
forming a plurality of stud bumps in a pattern having a geometrical shape on a surface of a substrate, the pattern defining a periphery of a bonding area on the surface of the substrate;
placing a solder material in the bonding area such that the solder material is surrounded by the stud bumps;
heating the solder material to a temperature where the solder material begins to flow within the bonding area;
pressing a bonding surface of a die onto the stud bumps with a sufficient pressure to crush the stud bumps a predetermined extent such that the solder material substantially evenly spreads between the stud bumps within the bonding area; and
solidifying the solder material to form a final solder area that conforms to the geometrical shape of the pattern of stud bumps.
2. The method of claim 1, wherein the stud bumps are formed in a circular pattern on the surface of substrate.
3. The method of claim 1, wherein the stud bumps are formed in a rectangular pattern on the surface of substrate.
4. The method of claim 1, wherein the stud bumps comprise gold, platinum, copper, or combinations thereof.
5. The method of claim 1, wherein the solder material is a spherical shaped preform.
6. The method of claim 1, wherein the solder material is a rectangular shaped preform.
7. The method of claim 1, wherein the solder material is a cylindrical shaped preform.
8. The method of claim 1, wherein the die comprises a micro-electro-mechanical systems (MEMS) sensor, an inertial sensor, or a laser diode.
9. The method of claim 1, wherein the substrate comprises a ceramic material, a plated metal, or a printed circuit board.
10. The method of claim 1, wherein the substrate comprises aluminum oxide, aluminum nitride, silicon nitride, silicon, or glass.
11. A semiconductor device, comprising:
a substrate having an upper surface; and
a die attached to the substrate at a controlled solder bond area that includes a solder material that is substantially evenly spread between a plurality of stud bumps coupled between the substrate and the die;
wherein the stud bumps are coupled in a pattern having a geometrical shape and define a periphery of the solder bond area;
wherein the solder material conforms to the geometrical shape of the pattern of the stud bumps.
12. The semiconductor device of claim 11, wherein the stud bumps are coupled in a circular pattern.
13. The semiconductor device of claim 11, wherein the stud bumps are coupled in a rectangular pattern.
14. The semiconductor device of claim 11, wherein the stud bumps comprise gold, platinum, copper, or combinations thereof.
15. The semiconductor device of claim 11, wherein the die comprises a MEMS sensor.
16. The semiconductor device of claim 11, wherein the die comprises an inertial sensor.
17. The semiconductor device of claim 11, wherein the die comprises a laser diode.
18. The semiconductor device of claim 11, wherein the substrate comprises a ceramic material, or a plated metal.
19. The semiconductor device of claim 11, wherein the substrate comprises aluminum oxide, aluminum nitride, silicon nitride, silicon, or glass.
20. The semiconductor device of claim 11, wherein the substrate comprises a printed circuit board.
Images & Drawings included:
Sources:
- United States Patent and Trademark Office - verify current appl. status at the USPTO↗
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