Package on package configuration

Description

BACKGROUND

Technical Field

The present invention relates to a package on package configuration, especially relates to a package substrate having a plurality of copper pillars configured on high density side and fabricated according to integrated circuit (IC) design rule.

Description of Related Art

FIG. 1 shows a prior art U.S. Pat. No. 9,153,560

FIG. 1 shows a prior art which discloses a package on package (PoP) integrated device. The integrated device 1100 includes a first package 1102 and a second package 1104. The first package 1102 includes a first substrate 1106, a first die (e.g., chip) 1108, an encapsulation material 1112, a first set of solder balls 1116, a first set of interconnects 1118, and a first set of package interconnects 1128 (e.g., copper pillar). The second package 1104 includes a second substrate 1105, a second die 1107 a third die 1109, a fourth die 1137, a fifth die 1139, a sixth die 1157, a seventh die 1159, a eighth die 1167, a ninth die 1169, a second set of solder balls 1115, a second set of interconnect 1117, a third set of interconnects 1119, a fourth set of interconnects 1147, and a fifth set of interconnects 1149. The second package 1104 is positioned above the first package 1102.

The prior art described a redistribution circuitry fabricated according a single rule within the substrate 1105, 1106 which cannot be applied to the instant invention comprising a package substrate with at least two redistribution circuitry fabricated according to different design rules.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a prior art

FIGS. 2A-2J show a fabrication process for a package on package configuration according to the present invention.

DETAILED DESCRIPTION OF THE INVENTION

A first IC package has a plurality of top metal pads configured according to IC design rule. A plurality of copper pillars are configured on the top side of the IC package. A second IC package has a plurality of bottom metal pads configured according to IC design rule. The second IC package is stacked on a top side of the first IC package, the second IC package is electrically couples to the first IC package through the plurality of copper pillars which is fabricated according to IC design rule.

FIGS. 2A-2J show a fabrication process for a package on package configuration according to the present invention.

FIG. 2A shows:

preparing a temporary carrier 100 with a release layer 101 on a top side of the temporary carrier 100;

forming a first dielectric layer 19D on a top side of the release layer 101;

fabricating a first redistribution circuitry 11 according to PCB design rule; the first redistribution circuitry 11 having a plurality of first bottom metal pads 1B and a plurality of first top metal pads 1T; a plurality of first metal via 1V electrically coupling the first bottom metal pads 1B to the first top metal pads 1T; each of the first metal vias has a shape with top wide bottom narrow.

FIG. 2B shows:

fabricating a second redistribution circuitry 21 according to IC design rule on a top side of the first redistribution circuitry 11; the second redistribution circuitry 21 having a plurality of second bottom metal pads 2B and a plurality of second top metal pads 2T, a plurality of second metal via 2V electrically coupling the second bottom metal pads 2B to the second top metal pads 2T; each of the second metal vias 2V has a shape with top wide bottom narrow;

at least one first dielectric layer 12 embedding the first redistribution circuitry 11 to form a first redistribution layer RDL1; and at least one second dielectric layer 22 embedding the second redistribution circuitry 21 to form a second redistribution layer RDL2.

FIG. 2C shows:

configuring a plurality of copper pillars 25 on a top side of the second top metal pads 2T among the plurality of second top metal pads 2T of the second redistribution circuitry 21.

FIG. 2D shows:

applying a dielectric layer 23 to embed the at least one first chip 20 to form a first IC package 1P.

FIG. 2E shows:

flattening a top side of the dielectric layer 23 and the plurality copper pillars 25.

FIG. 2F shows:

preparing a second IC package 2P, in a later step the second IC package shall stack on a top side of the first IC package; the second IC package 2P comprising a third redistribution circuitry 31 configured according to IC design rule, the third redistribution circuitry 31 embedded in at least one third dielectric layer 32, the third redistribution circuitry 31 and the at least one third dielectric layer 32 forming a third redistribution layer RDL3; the third redistribution circuitry 31 having a plurality of third bottom metal pads 3B on a bottom side and a plurality of third top metal pads 3T on a top side, and at least one second chip 30 configured on a top side of the third redistribution circuitry 31 and embedded in a molding compound 33. A plurality of metal contacts 35, such as copper pillars, configured on a bottom side of the third redistribution circuitry 31.

FIG. 2G shows:

stacking the second IC package 2P on a top side of the first IC package 1P. Each of the plurality of metal contacts 35 electrically coupled to a corresponding first copper pillar 25 among the plurality of first copper pillars 25. A gap 351 is formed between the second IC package and the first IC package, the gap 351 has a space height roughly equals to a height of the plurality of metal contacts 35.

FIG. 2H shows:

removing the temporary carrier 100 from a bottom side of the first redistribution circuitry 11, and

forming a plurality of opening 191 from a bottom side of the dielectric layer 19. Each opening 191 exposes a bottom surface of a corresponding first metal pad 1B among the plurality of first bottom metal pad 1B.

FIG. 2I shows:

planting a plurality of solder balls 192, each solder 192 configured on a bottom side of a corresponding first bottom metal pad 1B among the plurality of first bottom metal pads 1B.

FIG. 2J shows:

filling a bonding material 254 in the gap 253 to enhance the bounding strength therebetween.

While several embodiments have been described by way of example, it will be apparent to those skilled in the art that various modifications may be configured without departs from the spirit of the present invention. Such modifications are all within the scope of the present invention, as defined by the appended claims.