ELECTROPLATING PROCESS USING A PROXIMITY MASK WITH AN OVERHANG AND AN APPARATUS FOR PERFORMING THE SAME

Description

BACKGROUND

The edge terminal effect in an electrochemical plating (ECP) process produces a thickness increase at the edge regions of a wafer, which may degrade metal thickness uniformity, may increase topography of dielectric surfaces, and/or may decrease process yield.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 is a top-down view of a wafer that may be used in various embodiment electroplating processes of the present disclosure.

FIGS. 2A-2C are sequential vertical cross-sectional views of a region of a die in an a first embodiment structure of the wafer prior to performing an electroplating process according to an embodiment of the present disclosure.

FIG. 3A is schematic view of an electroplating apparatus of the present disclosure during an electroplating process that is performed on the first embodiment structure of the wafer according to an embodiment of the present disclosure.

FIG. 3B is a magnified vertical cross-sectional view of a region of a die in the first embodiment at the processing step of FIG. 3A.

FIG. 3C is a top-down view of the electroplating apparatus along an axial direction of the wafer at the processing step of FIGS. 3A and 3B.

FIGS. 3D and 3E are magnified vertical cross-sectional views of a region of a die for alternative configurations of the electroplating apparatus according to embodiments of the present disclosure.

FIGS. 4A and 4B are sequential vertical cross-sectional views of a region of a die in the first embodiment structure of the wafer after the electroplating process according to an embodiment of the present disclosure.

FIGS. 5A-5C are sequential vertical cross-sectional views of a region of a die in an a second embodiment structure of the wafer prior to performing an electroplating process according to an embodiment of the present disclosure.

FIG. 6A is schematic view of an electroplating apparatus of the present disclosure during an electroplating process that is performed on the second embodiment structure of the wafer according to an embodiment of the present disclosure.

FIG. 6B is a magnified vertical cross-sectional view of a region of a die in the second embodiment at the processing step of FIG. 6A.

FIG. 6C is a top-down view of the electroplating apparatus along an axial direction of the wafer at the processing step of FIGS. 6A and 6B.

FIGS. 6D and 6E are magnified vertical cross-sectional views of a region of a die for alternative configurations of the electroplating apparatus according to embodiments of the present disclosure.

FIGS. 7A and 7B are sequential vertical cross-sectional views of a region of a die in the second embodiment structure of the wafer after the electroplating process according to an embodiment of the present disclosure.

FIG. 8 is a first flow chart illustrating operational steps for an electroplating process of the present disclosure.

FIG. 9 is a second flow chart illustrating operational steps for an electroplating process of the present disclosure.

DETAILED DESCRIPTION

The present disclosure is directed to a an electroplating process using a proximity mask with an overhang and an apparatus for performing the same, the various aspects of which are described herebelow.

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. Drawings are not drawn to scale. Elements with the same reference numerals refer to the same element, and are presumed to have the same material composition and the same thickness range unless expressly indicated otherwise. Embodiments are expressly contemplated in which multiple instances of any described element are repeated unless expressly stated otherwise. Embodiments are expressly contemplated in which non-essential elements are omitted even if such embodiments are not expressly disclosed but are known in the art.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

According to an aspect of the present disclosure, a proximity mask may be used during an electroplating process to inhibit the edge terminal effect and to generate a lateral electrical field component at a periphery of a plating area. The lateral electrical field component tilts the direction of the electrical field, and reduces the magnitude of the electrical field in peripheral regions of the wafer in the plating path. The uniformity of the electroplated metal may be enhanced. A small separation distance between the proximity mask and the wafer may increase the effectiveness of the electrical field modification. The various aspects of the present disclosure are described in detail herebelow.

Referring to FIG. 1, a top-down view of a wafer 1000 is illustrated. The wafer includes a two-dimensional array of dies 100, which may be a two-dimensional periodic array such as a rectangular array. In one embodiment, each die 100 may comprise a redistribution structure that may be used as an interposer upon dicing of the wafer 1000. In an embodiment, the wafer 1000 may comprise a two-dimensional array of redistribution structures located on a carrier substrate 209. Each of the redistribution structures may comprise at least one respective redistribution dielectric layer and respective redistribution wiring interconnects. In an alternative embodiment, each die 100 may comprise a semiconductor die including a respective set of semiconductor devices (such as field effect transistors) therein. In one embodiment, the wafer 1000 comprises a two-dimensional array of semiconductor dies, and each of the semiconductor dies may comprise a respective set of semiconductor devices and metal interconnect structures. The diameter of the wafer 1000 may be in a range from 150 mm to 450 mm, although lesser and greater diameters may also be used.

FIGS. 2A-2C are sequential vertical cross-sectional views of a region of a die 100 in an a first embodiment structure of the wafer 1000 prior to performing an electroplating process according to an embodiment of the present disclosure.

Referring to FIG. 2A, the wafer 1000 may comprise a carrier substrate 209 and redistribution structures formed thereupon. In one embodiment, the wafer 1000 may comprise a two-dimensional array of redistribution structures (218, 228, 210, 220, 230) located on a carrier substrate 209. Each of the redistribution structures (218, 228, 210, 220, 230) may comprise at least one respective redistribution dielectric layer (210, 220, 230) and respective redistribution wiring interconnects (218, 228). The carrier substrate 209 may comprise a glass substrate or a semiconductor substrate that may provide sufficient mechanical support to the structures to be subsequently formed thereupon. In one embodiment, the thickness of the carrier substrate 209 may be in a range from 300 microns to 1 mm, although lesser and greater thicknesses may also be used. An adhesive layer 207 may be optionally formed on the top surface of the carrier substrate 209.

The redistribution dielectric layers (210, 220, 230) and the redistribution wiring interconnects (218, 228) may be formed over the carrier substrate 209. In the illustrated example, the redistribution dielectric layers (210, 220, 230) comprise a first redistribution dielectric layer 210, a second redistribution dielectric layer 220, and a third redistribution dielectric layer 230. The redistribution wiring interconnects (218, 228) may comprise first redistribution wiring interconnects 218 that are formed after formation of the first redistribution dielectric layer 210 and prior to formation of the second redistribution dielectric layer 220, and second redistribution wiring interconnects 228 that are formed after formation of the second redistribution dielectric layers 220 and prior to formation of the third redistribution dielectric layer 230. Via openings 239 may be formed in the third redistribution dielectric layer 230 such that top surface segments of the second redistribution wiring interconnects 228 are exposed underneath each opening.

While the present disclosure is described using an embodiment in which an electroplating process is performed to form third redistribution wiring interconnects over the third redistribution dielectric layers 230, it is to be understood that the electroplating process of the present disclosure may be performed to form redistribution wiring interconnects at any level. Thus, the first redistribution wiring interconnects 218, the second redistribution wiring interconnects 228, and/or any other upper-level redistribution wiring interconnects to be formed after formation of the third redistribution wiring interconnects may be fabricated using the electroplating process of the present disclosure. Thus, the selection of the third redistribution wiring interconnects for description of the electroplating process of the present disclosure does not mean that the electroplating process of the present disclosure may be performed only at the level of the third redistribution wiring interconnects, but means that the electroplating process of the present disclosure may be performed at any level for the purpose of formation of redistribution wiring interconnects.

Generally, each redistribution dielectric layer (210, 220, 230) may be formed by application of a dielectric polymer material such as polyimide (PI), benzocyclobutene (BCB), or polybenzobisoxazole (PBO), for example, by spin coating. Generally, the thickness of each redistribution dielectric layer (210, 220, 230) may be in a range from 2 microns to 40 microns, such as from 4 microns to 20 microns, although lesser and greater thicknesses may also be used. Upon curing of each redistribution dielectric layer (210, 220, 230), a photoresist layer (not shown) may be applied over a respective redistribution dielectric layer (210, 220, 230), and may be subsequently patterned to form openings. In embodiments in which underlying redistribution wiring interconnects (218, 228) are present under the respective redistribution dielectric layer (210, 220, 230), the openings in the photoresist layer may be formed over areas of the underlying redistribution wiring interconnects (218, 228). An anisotropic etch process may be performed to transfer the pattern of the openings in the photoresist layer through the respective redistribution dielectric layer (210, 220, 230). Via openings are formed through the respective redistribution dielectric layer (210, 220, 230). The photoresist layer may be subsequently removed, for example, by ashing.

Each of the redistribution wiring interconnects (218, 228) illustrated in FIG. 2A and any additional redistribution wiring interconnects to be subsequently formed may be fabricated by using a sequence of processing steps, which include formation of a metallic seed layer, formation of a patterned photoresist layer, an electroplating process, removal of the patterned photoresist layer, and a recess etch process that removes unmasked portions of the metallic seed layer. For example, each of the redistribution wiring interconnects (218, 228) illustrated in FIG. 2A and any additional redistribution wiring interconnects to be subsequently formed may be fabricated by performing a sequence of processing steps described with reference to FIGS. 2B, 2C, 3A-3E, 4A, and 4B. In other words, the sequence of processing steps described with reference to FIGS. 2B, 2C, 3A-3E, 4A, and 4B may be used not only to form third redistribution wiring interconnects on the third redistribution dielectric layer 230, but may also be used, with necessary changes in process details, to form the first redistribution wiring interconnects 218, to form the second redistribution wiring interconnects 228, and/or to form additional redistribution wiring interconnects that may be fabricated after formation of the third redistribution wiring interconnects.

Referring to FIG. 2B, a metallic seed layer 52L may be formed on a top surface of the wafer 1000 including the two-dimensional array of dies 100. The metallic seed layer 52L may comprise a layer stack of a barrier metal layer 521 and a copper seed layer. The barrier metal layer 521 comprises a barrier metallic material such as Ti, Ta, TiN, TaN, WN, or a combination thereof. The barrier metallic material functions as a diffusion-blocking barrier for copper to be subsequently deposited. The barrier metal layer 521 may be deposited by a conformal or a non-conformal deposition process. For example, the barrier metal layer 521 may be deposited by physical vapor deposition (PVD) or chemical vapor deposition (CVD). The thickness of the barrier metal layer 521 may be in a range from 3 nm to 300 nm such as from 10 nm to 100 nm and/or from 20 nm to 50 nm, although lesser and greater thicknesses may also be used. The copper seed layer 522 comprises, and/or consists essentially of, copper. The copper seed layer 522 may be deposited, for example, by physical vapor deposition. The thickness of the copper seed layer 522 may be in a range from 100 nm to 1,000 nm, such as from 200 nm to 500 nm, although lesser and greater thicknesses may also be used.

Referring to FIG. 2C, a patterned photoresist layer 47 may be formed over the metallic seed layer 52L. The thickness t of the patterned photoresist layer 47 is at least the target plating thickness of the electroplating process to be subsequently performed. For example, the target plating thickness of the electroplating process may be in a range from 2 microns to 40 microns, such as from 4 microns to 20 microns, although lesser and greater target plating thicknesses may also be used. The thickness t of the patterned photoresist layer 47 may be in a range from 105% to 120% of the target plating thickness. The pattern of the openings in the patterned photoresist layer 47 may be the same as the pattern of the third redistribution wiring interconnects to be subsequently formed. Thus, the areas of the openings in the patterned photoresist layer may generally include the areas of the via openings 239 illustrated in FIG. 2A.

Generally, the thickness t of the patterned photoresist layer 47 is greater than the target plating thickness of the electroplating process to be subsequently used. However, the actual plating thickness of an electroplated material (such as copper) may have local variations. Specifically, electroplating apparatus known in the art tend to provide a greater thickness at peripheral regions of a wafer compared to a central region of the wafer. It is also known that the periphery-to-edge variations of the thickness of an electroplated material may be greater than 30%, and/or greater than 40%, and or greater than 50% of the target electroplating thickness. Under such conditions, an electroplated material may be formed over peripheral areas of a top surface of a patterned photoresist layer to provide a mushroom-shaped vertical cross-sectional profile for the electroplated material. Such mushroom-shaped profiles may cause severe problems in the topography of a redistribution structure, and may cause gaps during formation of an overlying redistribution dielectric layer. Embodiments of the present disclosure may be used to increase the thickness uniformity of an electroplated material, and to ensure that mushroom-shaped profiles of the electroplated material may be avoided.

FIG. 3A is schematic view of an electroplating apparatus of the present disclosure during an electroplating process that is performed on the first embodiment structure of the wafer 1000 according to an embodiment of the present disclosure. FIG. 3B is a magnified vertical cross-sectional view of a region of a die 100 in the first embodiment at the processing step of FIG. 3A. FIG. 3C is a view of the electroplating apparatus along an axial direction AD of the wafer 1000 at the processing step of FIGS. 3A and 3B. FIGS. 3D and 3E are magnified vertical cross-sectional views of a region of a die 100 for alternative configurations of the electroplating apparatus according to embodiments of the present disclosure.

FIGS. 3A-3E illustrate various configurations of an electroplating apparatus according embodiments of the present disclosure. The electroplating apparatus is illustrated after loading a wafer 1000, such as the wafer 1000 described with reference to FIG. 2C, therein and after performing an electroplating process. The wafer 1000 may comprise the carrier substrate 209 and the two-dimensional array of redistribution structures thereupon.

Generally, the electroplating apparatus may include a wafer holder 20 comprising a flat front surface, a wafer clamp assembly (120, 122, 130), an electroplating bath 300, an anode 140, at least one cathode contact lead 110, and a process controller 200. The wafer clamp assembly (120, 122, 130) includes a wafer clamp frame 120 which is configured to press against a wafer 1000 toward the front flat surface of the wafer holder 20, and has an inner sidewall 121 that is laterally offset from a symmetry axis SA that is perpendicular to the flat front surface by a first radial distance rd1. The symmetry axis SA is an axis of rotational symmetry for the wafer holder 20. The direction of the symmetry axis SA is herein referred to as an axial direction AD. The wafer clamp assembly (120, 122, 130) further includes a dielectric seal ring 122 located on a backside of the wafer clamp frame 120 and facing the flat front surface of the wafer holder 20. According to an aspect of the present disclosure, the wafer clamp assembly (120, 122, 130) comprises a proximity mask 130 comprising a conductive material and having a cylindrical inner sidewall 131 that is laterally offset from the symmetry axis SA by a second radial distance rd2 that is less than the first radial distance rd1.

The electroplating bath 300 is configured to hold an electroplating solution 310, a wafer 1000, the wafer clamp assembly (120, 122, 130), and the anode 140 therein. The anode 140 may comprise a conductive plate that is spaced from the wafer holder 20 along the axial direction AD by a uniform spacing. The area of the anode, as seen along the axial direction AD, may include the entirety of the area of the wafer holder 20. The at least one cathode contact lead 110 may be configured to press against a peripheral front surface of the wafer 1000, and may be located outside an annular contact area between the dielectric seal ring 122 and the wafer 1000.

The process controller 200 is configured to electrically bias the anode 140, the proximity mask 130, and the cathode contact lead 110 such that electrical field within a predominant fraction (i.e., not less than 50%) of an entire volume of an annular region AR has a distribution (i.e., a statistical distribution) of a tilt angle (α or β) relative to the axial direction AD that is greater than arctangent(0.1) under a condition in which a conductive material layer (such as a metallic seed layer 52L) is present on a front side of the wafer 1000. The tilt angle (α or β) may be measured relative to the axial direction AD such that the tilt angle (α or β), measured in units of a radian, has a value in a range between 0 and π/2. In embodiments in which the electrical field E has an axial component pointing along a direction from the anode 140 toward the wafer holder 20, the tilt angle is referred to as a first tilt angle α. In embodiments in which the electrical field has an axial component pointing along a direction from the wafer holder 20 toward the anode 140, the tilt angle is referred to as a second tilt angle β.

The annular region AR is defined as a region that is radially offset from the symmetry axis SA by a radial distance that is greater then the first radial distance rd1 and is less than the second radial distance rd2, and is bounded by the wafer 1000 and by the proximity mask 130 along an axial direction AD that is parallel to a direction of the symmetry axis SA. Generally, the first tilt angles α are present in the annular region AR in proximity to the wafer 1000, and the second tilt angles β are present in proximity to the physically exposed annular backside surface 133 of the proximity mask 130. The taper angle of the electrical field E outside the volumes of the annular region AR and in proximity to a cylindrical inner sidewall 131 of the proximity mask 130 is herein referred to as a third taper angle γ. The electrical field E in proximity to the cylindrical inner sidewall 131 of the proximity mask 130 may have an axial component that points from the wafer holder 20 toward the anode 140. Generally, in a predominant fraction of the volume between the anode 140 and the wafer 1000 that is laterally spaced from the symmetry axis SA by a radial distance less than the second radial distance rd1 may have a uniform electrical field that is parallel to the axial direction AD and having a same magnitude throughout. The uniform electrical field has an axial component that is parallel to a direction from the anode 140 toward the wafer holder 20.

In one embodiment, the proximity mask 130 may be in contact with a front surface of the wafer clamp frame 120. In one embodiment, the front surface of the wafer clamp frame 120 may be an annular surface having a circular inner periphery of a radius that equals the second radial distance rd2. The annular surface may have a circular outer periphery of a radius that is greater than the radius R of the wafer 1000. In one embodiment, the first radial distance rd1 is greater than the second radial distance rd2 by a radial distance difference rdd that is in a range from 1% to 20% of a radial distance between a tip of the cathode contact lead 110 and the symmetry axis SA.

In one embodiment, the electroplating apparatus may be configured to position a backside surface of the proximity mask 130 within a two-dimensional plane that is uniformly spaced from the flat front surface of the wafer holder 20 by a distance that equals the sum of an axial gap distance agd and a thickness of the wafer 1000. The axial gap distance agd is the distance along the axial direction AD between the annular backside surface 133 of the proximity mask 130 and the front surface of the wafer 1000, which may be a physically exposed surface of the patterned photoresist layer 47. In one embodiment, the difference between the first radial distance rd1 and the second radial distance rd2 is greater than the axial gap distance agd.

The annular backside surface 133 that faces the front surface of the wafer 1000 may be flush with the distal annular surface of the wafer clamp frame 120 as illustrated in FIGS. 3A and 3B, or may be more proximal to the front surface of the wafer 1000 (such as the physically exposed planar surface of the patterned photoresist layer 47) than the Euclidean plane including the distal annular surface of the wafer clamp frame 120 that contacts the proximity mask 130 as illustrated in FIGS. 3D and 3E. In this embodiment, the proximity mask 130 may comprise an annular protrusion portion 138 that is more proximal to the front surface of the wafer 1000 than the Euclidean plane including the distal annular surface of the wafer clamp frame 120 that contacts the proximity mask 130. The annular backside surface 133 may be adjoined to the inner sidewall 121 of the wafer clamp frame 120 as illustrated in FIG. 3D, or may be laterally spaced from the inner sidewall 121 of the wafer clamp frame 120 as illustrated in FIG. 3E. In the embodiments shown in FIGS. 3D and 3E (as well as FIGS. 6D and 6E discussed in more detail below), the vertical distance between annular backside surface 133 and the horizontal plane including the interface between the wafer clamp frame 120 and the proximity mask 130 may be used as a tuning parameter for fine-tuning the electrical field distribution in the annular region AR. Further, the lateral distance between the inner sidewall of the wafer clamp frame 120 and the outer periphery of the annular backside surface 133 may be used as a tuning parameter for fine-tuning the electrical field distribution in the annular region AR.

A metal such as copper may be electroplated on the wafer 1000, such as the wafer described with reference to FIG. 2C, in the following manner. The wafer 1000 may be mounted on the wafer holder 20 using the wafer clamp assembly (120, 122, 130). As discussed above, the wafer clamp assembly (120, 122, 130) comprises the wafer clamp frame 120, the dielectric seal ring 122, and the proximity mask 130. The wafer clamp frame 120 may have an inner sidewall 121 that is laterally offset from a symmetry axis SA passing through a geometrical center GC of the wafer 1000 and is perpendicular to a backside surface BS of the wafer 1000 by a first radial distance rd1 that equals a radius R of the wafer 1000 less a first edge offset distance eod1. The dielectric seal ring 122 is interposed between the wafer clamp frame 120 and the wafer 1000. The proximity mask 130 comprises a conductive material and has a cylindrical inner sidewall 131 that is laterally offset from the symmetry axis SA by a second radial distance rd2 that equals the radius R of the wafer 1000 less a second edge offset distance eod2. The cylindrical inner sidewall 131 radially protrudes inward from an inner sidewall 121 of the wafer clamp frame 120 such that an annular region AR is provided between an annular backside surface 133 of the proximity mask 130 and a front side of the wafer 1000.

The proximity mask 130 may be in contact with a front surface of the wafer clamp frame 120, and may contact the entirety of the front surface of the wafer clamp frame. The second edge offset distance eod2 is greater than the first edge offset distance eod1 by a radial distance difference rdd that is in a range from 1% to 20% of the radius R of the wafer 1000. In an illustrative example, the radius R of the wafer 1000 may be in a range from 75 mm to 225 mm, the first lateral offset distance eod1 may be in a range from 1 mm to 5 mm, such as from 2 mm to 4 mm, and the second lateral offset distance eod2 may be in a range from 2 mm to 20 mm, such as from 4 mm to 15 mm, although lesser and greater dimensions may also be used. The radial distance difference rdd may be in a range from 2 mm to 15 mm, such as from 3 mm to 12 mm, although lesser and greater dimensions may also be used.

In one embodiment, the proximity mask 130 comprises an annular backside surface 133 that faces a front surface of the wafer 1000 and is spaced from the front surface of the wafer 1000 by an axial gap distance agd. The axial gap distance agd may be in a range from 1 mm to 10 mm, such as from 2 mm to 8 mm, although lesser and greater dimensions may also be used. In one embodiment, the axial gap distance agd may be greater than 1.0% of the radius R of the wafer 1000 and may be less than 10% of the radius R of the wafer 1000. The spacing along the axial direction AD between the proximity mask 130 and the wafer 1000 may be less than a spacing along the axial direction AD between the proximity mask 130 and the anode 140 during the electroplating process. In one embodiment, the ratio of the radial distance difference rdd to the axial gap distance agd may be in a range from 1 to 5, such as from 1.5 to 4.5, and/or from 2.0 to 4.0.

In one embodiment, the wafer 1000 comprises a two-dimensional array of redistribution structures (218, 228, 210, 220, 230) located on a carrier substrate 209, and each of the redistribution structures (218, 228, 210, 220, 230) comprises at least one respective redistribution dielectric layer (210, 220, 230) and respective redistribution wiring interconnects (218, 228). In one embodiment, the entire area of at least one die 100 selected from the two-dimensional array of dies 100 has an areal overlap with the proximity mask 130, and does not have any areal overlap with a circular opening in the proximity mask 130 in a plan view along the axial direction AD.

The electroplating process may be performed in an electroplating bath 300 while the wafer holder 20 and the wafer 1000 are immersed in the electroplating solution 310 and while the proximity mask 130 is electrically biased such that electrical field within a predominant fraction of an entire volume of the annular region AR has a distribution of a tilt angle (α or β) relative to the axial direction AD that is greater than arctangent(0.1). Arctangent(0.1) is about 0.0997 radian, which is about 5.71 degrees. The axial direction AD is parallel to the symmetry axis SA of the wafer 1000. The symmetry axis SA is perpendicular to the backside surface BS of the wafer 1000 and passes through the geometrical center GC of the wafer 1000. The annular region AR is defined as a region that is radially offset from the symmetry axis SA by a radial distance that is greater then the first radial distance rd1 and is less than the second radial distance rd2, and is bounded by the wafer 1000 and by the proximity mask 130 along an axial direction AD that is parallel to a direction of the symmetry axis SA.

In one embodiment, the electrical field within more than 60%, and/or more than 70%, and/or more than 80%, and or 90%, of the entire volume of the annular region AR has a distribution of a tilt angle (α or β) relative to the axial direction AD that is greater than arctangent(0.1). Arctangent(0.1) is about 0.0997 radian, which is about 5.71 degrees. The electrical field within a predominant fraction (i.e., at least 50%) of the entire volume of the annular region AR has a distribution of a tilt angle (α or β) relative to the axial direction AD that is greater than arctangent(0.2), and/or may be greater than arctan(0.3). Arctangent(0.2) is about 0.1974 radian, which is about 11.31 degrees. Arctangent(0.3) is about 0.2915 radian, which is about 16.70 degrees.

In one embodiment, an annular backside surface 133 of the proximity mask 130 is exposed to the electroplating bath, and faces a front side of the wafer 1000. The dielectric seal ring 122 contacts the patterned photoresist layer 47, and the at least one cathode contact lead 110 contacts a front surface of the metallic seed layer 52L outside an annular contact area between the dielectric seal ring 122 and the metallic seed layer 52L. Each cathode contact lead 110 may be electrically connected to the metallic seed layer 52L. for example, by pressing against the physically exposed surface of the metallic seed layer in a peripheral region of the wafer 1000 that is located outside the annular contact area between the dielectric seal ring 122 and the wafer 1000. The anode 140 is exposed to the electroplating solution 310.

Each cathode contact lead 110 may be electrically biased at a negative voltage relative to the anode 140. The voltage applied to each cathode contact lead 110 may be in a range from −1 V to −10 V, such as from −1.5 V to −5V, although lesser and greater bias voltages may also be used. The proximity mask 130 is electrically biased at a more negative voltage relative to the cathode contact lead 110 during the electroplating process. For example, the voltage applied to the proximity mask 130 as measured relative to the voltage applied to the at least one cathode contact lead 110 may be in a range from −0.01 V to −1.0 V, such as from −0.05 V to −0.5 V, although lesser and greater voltages may also be used.

Electroplated material portions 54 may be formed within the openings in the patterned photoresist layer 47. In one embodiment, the electroplated material portions 54 may be copper portions consisting essentially of copper. The thickness of each electroplated material portions 54 may be in a range from 2 microns to 40 microns, such as from 4 microns to 20 microns, although lesser and greater thicknesses may also be used.

Generally, the electric field distribution within the annular region AR of the present disclosure reduces the normal component of the electrical field at the growth surface of the electroplated material portions 54, and reduces the growth rate of the electroplated material at the growth surfaces of the electroplated material portions 54. According to an aspect of the present disclosure, the reduction in growth rate of the electroplated material in proximity to the annular region AR may be advantageously used to provide more uniform deposition rate for the electroplated material across the entirety of the front surface of the wafer 1000 relative to comparative exemplary electroplating processes that does not use an annular region axially bounded by the front surface of the wafer 1000 and the annular backside surface 133 of the proximity mask 130. In an illustrative example, for a wafer having a radius of 150 mm, a thickness nonuniformity less than 25% may be achieved using the apparatus of the present disclosure. The thickness nonuniformity may be defined as (the maximum thickness−the minimum thickness)/(the maximum thickness+the minimum thickness).

Referring to FIG. 4A, the wafer 1000 may be extracted from the electroplating apparatus illustrated in FIGS. 3A-3E. The patterned photoresist layer 47 may be removed, for example, by performing an ashing process.

Referring to FIG. 4B, an etch back process may be performed to remove unmasked portions of the metallic seed layer 52L. The etch back process may comprise a wet etch process or a reactive ion etch process. Each remaining patterned portion of the metallic seed layer 52L is herein referred to as a metallic seed layer 52. Each remaining contiguous combination of a metallic seed layer 52 and an electroplated material portion 54 constitutes a metallic structure 56, which may be a third redistribution wiring interconnect.

Subsequently, additional redistribution dielectric layers and additional redistribution wiring interconnects may be optionally formed. The carrier substrate 209 may be detached from the two-dimensional array of redistribution structures, and the two-dimensional array of redistribution structures may be diced into singulated redistribution structures, which may be organic interposers.

FIGS. 5A-5C are sequential vertical cross-sectional views of a region of a die 100 in an a second embodiment structure of the wafer 1000 illustrated in FIG. 1 prior to performing an electroplating process according to an embodiment of the present disclosure.

Referring to FIG. 5A, the wafer 1000 comprises a two-dimensional array of semiconductor dies 100, and each of the semiconductor dies 100 comprises a respective set of semiconductor devices 700 and a respective set of metal interconnect structures (612, 628, 622, 628, 632, 638, 642, 648). In one embodiment, the wafer 1000 may comprise a semiconductor substrate 609, which may be a commercially available silicon wafer. In this embodiment, the two-dimensional array of dies 100 in the wafer 1000 may comprise a two-dimensional array of semiconductor dies 100. The semiconductor dies 100 may be formed by formatting various semiconductor devices 700 and metal interconnect structures on the semiconductor substrate 609.

For example, shallow trench isolation structures 720 including a dielectric material such as silicon oxide may be formed in an upper portion of the semiconductor substrate 609. Suitable doped semiconductor wells, such as p-type wells and n-type wells, may be formed within each area that may be laterally enclosed by a portion of the shallow trench isolation structures 720. Field effect transistors may be formed over the top surface of the semiconductor substrate 609. For example, each field effect transistor may include a source region 732, a drain region 738, a semiconductor channel 735 that includes a surface portion of the semiconductor substrate 609 extending between the source region 732 and the drain region 738, and a gate structure 750. Each gate structure 750 may include a gate dielectric 752, a gate electrode 754, a gate cap dielectric 758, and a dielectric gate spacer 756. A source-side metal-semiconductor alloy region 742 may be formed on each source region 732, and a drain-side metal-semiconductor alloy region 748 may be formed on each drain region 738. While planar field effect transistors are illustrated in the drawings, embodiments are expressly contemplated herein in which the field effect transistors may additionally or alternatively include fin field effect transistors (FinFET), gate-all-around field effect (GAA FET) transistors, or any other type of field effect transistors (FETs). The semiconductor devices 700 may comprise such field effect transistors and additional types of semiconductor devices such as diodes, resistors, capacitors, inductors, etc.

Various metal interconnect structures formed within dielectric material layers may be subsequently formed over the semiconductor substrate 609 and the semiconductor devices 700. The dielectric material layers may include, for example, a contact-level dielectric material layer 601, a first metal-line-level dielectric material layer 610, a second line-and-via-level dielectric material layer 620, a third line-and-via-level dielectric material layer 630, a fourth line-and-via-level dielectric material layer 640, and a fifth line-and-via-level dielectric material layer 650. The metal interconnect structures may include device contact via structures 612 formed in the contact-level dielectric material layer 601 and contact a respective component of a CMOS circuitry, first metal line structures 618 formed in the first metal-line-level dielectric material layer 610, first metal via structures 622 formed in a lower portion of the second line-and-via-level dielectric material layer 620, second metal line structures 628 formed in an upper portion of the second line-and-via-level dielectric material layer 620, second metal via structures 632 formed in a lower portion of the third line-and-via-level dielectric material layer 630, third metal line structures 638 formed in an upper portion of the third line-and-via-level dielectric material layer 630, third metal via structures 642 formed in a lower portion of the fourth line-and-via-level dielectric material layer 640, fourth metal line structures 648 formed in an upper portion of the fourth line-and-via-level dielectric material layer 640, fourth metal via structures 652 formed in a lower portion of the fifth line-and-via-level dielectric material layer 650, and fifth metal line structures 658 formed in an upper portion of the fifth line-and-via-level dielectric material layer 650.

Each of the dielectric material layers (601, 610, 620, 630, 640, 650) may include a dielectric material such as undoped silicate glass, a doped silicate glass, organosilicate glass, amorphous fluorinated carbon, porous variants thereof, or combinations thereof. Each of the metal interconnect structures (612, 618, 622, 628, 632, 638, 642, 648, 652, 658) may include at least one conductive material, which may be a combination of a metallic liner layer (such as a metallic nitride or a metallic carbide) and a metallic fill material. Each metallic liner layer may include TiN, TaN, WN, TiC, TaC, and WC, and each metallic fill material portion may include W, Cu, Al, Co, Ru, Mo, Ta, Ti, alloys thereof, and/or combinations thereof. Other suitable materials within the contemplated scope of disclosure may also be used. In one embodiment, the first metal via structures 622 and the second metal line structures 628 may be formed as integrated line and via structures by a dual damascene process, the second metal via structures 632 and the third metal line structures 638 may be formed as integrated line and via structures, the third metal via structures 642 and the fourth metal line structures 648 may be formed as integrated line and via structures, and/or the fourth metal via structures 652 and the fifth metal line structures 658 may be formed as integrated line and via structures.

While the present disclosure is described using an embodiment in which an electroplating process is performed to form metal interconnect structures above the fifth line-and-via-level dielectric material layer 650, it is to be understood that the electroplating process of the present disclosure may be performed to form metal interconnect structures at any level. Thus, any of the metal interconnect structures (612, 618, 622, 628, 632, 638, 642, 648, 652, 658) located within, or below, the fifth line-and-via-level dielectric material layer 650, the metal interconnect structures to be formed in the sixth interconnect level, and/or any other metal interconnect structure to be formed thereabove may be fabricated using the electroplating process of the present disclosure. Thus, the selection of the sixth interconnect level for description of the electroplating process of the present disclosure does not mean that the electroplating process of the present disclosure may be performed only at the sixth interconnect level, but means that the electroplating process of the present disclosure may be performed at any level for the purpose of formation of redistribution wiring interconnects.

Referring to FIG. 5B, a metallic seed layer 52L may be formed on a top surface of the wafer 1000 including the two-dimensional array of dies 100. In the illustrated example, the metallic seed layer 52L may be formed on the top surface of the fifth line-and-via-level dielectric material layer 650 and on the top surfaces of the fifth metal line structures 658. The metallic seed layer 52L may comprise a layer stack of a barrier metal layer 521 and a copper seed layer. The barrier metal layer 521 comprises a barrier metallic material such as Ti, Ta, TiN, TaN, WN, or a combination thereof. The barrier metallic material functions as a diffusion-blocking barrier for copper to be subsequently deposited. The barrier metal layer 521 may be deposited by a conformal or a non-conformal deposition process. For example, the barrier metal layer 521 may be deposited by physical vapor deposition or chemical vapor deposition. The thickness of the barrier metal layer 521 may be in a range from 3 nm to 300 nm such as from 10 nm to 100 nm and/or from 20 nm to 50 nm, although lesser and greater thicknesses may also be used. The copper seed layer 522 comprises, and/or consists essentially of, copper. The copper seed layer 522 may be deposited, for example, by physical vapor deposition. The thickness of the copper seed layer 522 may be in a range from 100 nm to 1,000 nm, such as from 200 nm to 500 nm, although lesser and greater thicknesses may also be used.

Referring to FIG. 5C, a patterned photoresist layer 47 may be formed over the metallic seed layer 52L. The thickness t of the patterned photoresist layer 47 is at least the target plating thickness of the electroplating process to be subsequently performed. For example, the target plating thickness of the electroplating process may be in a range from 2 microns to 40 microns, such as from 4 microns to 20 microns, although lesser and greater target plating thicknesses may also be used. The thickness t of the patterned photoresist layer 47 may be in a range from 105% to 120% of the target plating thickness. The pattern of the openings 49 in the patterned photoresist layer 47 may be the same as the pattern of the third redistribution wiring interconnects to be subsequently formed. Thus, the areas of the openings 49 in the patterned photoresist layer may be formed within the areas of the fifth metal line structures 658.

Generally, the thickness t of the patterned photoresist layer 47 is greater than the target plating thickness of the electroplating process to be subsequently used. However, the actual plating thickness of an electroplated material (such as copper) may have local variations. Specifically, electroplating apparatus known in the art tend to provide a greater thickness at peripheral regions of a wafer compared to a central region of the wafer. It is also known that the periphery-to-edge variations of the thickness of an electroplated material may be greater than 30%, and/or greater than 40%, and or greater than 50% of the target electroplating thickness. Under such conditions, an electroplated material may be formed over peripheral areas of a top surface of a patterned photoresist layer to provide a mushroom-shaped vertical cross-sectional profile for the electroplated material. Such mushroom-shaped profiles may cause severe problems in the topography of a redistribution structure, and may cause gaps during formation of an overlying redistribution dielectric layer. Embodiments of the present disclosure may be used to increase the thickness uniformity of an electroplated material, and to ensure that mushroom-shaped profiles of the electroplated material may be avoided.

FIG. 6A is schematic view of an electroplating apparatus of the present disclosure during an electroplating process that is performed on the second embodiment structure of the wafer 1000 according to an embodiment of the present disclosure. FIG. 6B is a magnified vertical cross-sectional view of a region of a die 100 in the second embodiment at the processing step of FIG. 6A. FIG. 6C is a view of the electroplating apparatus along an axial direction AD of the wafer 1000 at the processing step of FIGS. 6A and 6B. FIGS. 6D and 6E are magnified vertical cross-sectional views of a region of a die 100 for alternative configurations of the electroplating apparatus according to embodiments of the present disclosure.

Generally, the electroplating apparatus illustrated in FIGS. 6A-6E may be the same as the electroplating apparatus illustrated in FIGS. 3A-3E with optional modifications in the dimensions to accommodate any size variation in the semiconductor wafer 609. Thus, a wafer 1000 comprising a two-dimensional array of semiconductor dies 100 may be loaded into the electroplating apparatus, and the processing steps described with reference to FIGS. 3A-3E may be performed to form electroplated material portions 54 within the areas of the openings in the patterned photoresist layer 47.

As described above, the electric field distribution within the annular region AR of the present disclosure reduces the normal component of the electrical field at the growth surface of the electroplated material portions 54, and reduces the growth rate of the electroplated material at the growth surfaces of the electroplated material portions 54. According to an aspect of the present disclosure, the reduction in growth rate of the electroplated material in proximity to the annular region AR may be advantageously used to provide more uniform deposition rate for the electroplated material across the entirety of the front surface of the wafer 1000 relative to comparative exemplary electroplating processes that does not use an annular region axially bounded by the front surface of the wafer 1000 and the annular backside surface 133 of the proximity mask 130. In an illustrative example, for a wafer having a radius of 150 mm, a thickness nonuniformity less than 25% may be achieved using the apparatus of the present disclosure. The thickness nonuniformity may be defined as (the maximum thickness−the minimum thickness)/(the maximum thickness+the minimum thickness).

Referring to FIG. 7A, the wafer 1000 may be extracted from the electroplating apparatus illustrated in FIGS. 6A-6E. The patterned photoresist layer 47 may be removed, for example, by performing an ashing process.

Referring to FIG. 7B, an etch back process may be performed to remove unmasked portions of the metallic seed layer 52L. The etch back process may comprise a wet etch process or a reactive ion etch process. Each remaining patterned portion of the metallic seed layer 52L is herein referred to as a metallic seed layer 52. Each remaining contiguous combination of a metallic seed layer 52 and an electroplated material portion 54 constitutes a metallic structure 56, which may be a third redistribution wiring interconnect.

Subsequently, additional dielectric material layers and additional metal interconnect structures may be optionally formed. The two-dimensional array of semiconductor dies 100 may be diced into discrete semiconductor dies 100 by singulation, i.e., by cutting through the dielectric material layers (601, 610, 620, 630, 640, 650) and the semiconductor substrate 609.

FIG. 8 is a first flow chart illustrating operational steps for an electroplating process of the present disclosure.

Referring to step 810 and FIGS. 1, 2A, 2B, 5A, and 5B, a metallic seed layer 52L may be deposited on a top surface of a wafer 1000 including a two-dimensional array of dies 100.

Referring to step 820 and FIGS. 2C, 3A-3E, 5C, and 6A-6E, the wafer 1000 may be mounted on a wafer holder 20 using a wafer clamp assembly (120, 122, 130). The wafer clamp assembly (120, 122, 130) comprises a wafer clamp frame 120 having an inner sidewall 121 that is laterally offset from a symmetry axis SA passing through a geometrical center GC of the wafer 1000 and is perpendicular to a backside surface BS of the wafer 1000 by a first radial distance rd1 that equals a radius R of the wafer 1000 less a first edge offset distance eod1. The wafer clamp assembly (120, 122, 130) further comprises a dielectric seal ring 122 interposed between the wafer clamp frame 120 and the wafer 1000, and a proximity mask 130 comprising a conductive material and having a cylindrical inner sidewall 131 that is laterally offset from the symmetry axis SA by a second radial distance rd2 that equals the radius R of the wafer 1000 less a second edge offset distance eod2.

Referring to step 830 and FIGS. 3A-3E, 4A, 4B, 6A-6E, 7A, and 7B, an electroplating process may be performed in an electroplating bath 300 while the wafer holder 20 and the wafer 1000 are immersed in an electroplating solution 310 and while the proximity mask 130 is electrically biased such that electrical field within a predominant fraction of an entire volume of an annular region AR has a distribution of a tilt angle (α or β) relative to the axial direction AD that is greater than arctangent(0.1). The annular region AR is defined as a region that is radially offset from the symmetry axis SA by a radial distance that is greater then the first radial distance rd1 and is less than the second radial distance rd2, and is bounded by the wafer 1000 and by the proximity mask 130 along an axial direction AD that is parallel to a direction of the symmetry axis SA.

FIG. 9 is a second flow chart illustrating operational steps for an electroplating process of the present disclosure.

Referring to step 910 and FIGS. 1, 2A, 2B, 5A, and 5B, a metallic seed layer 52L may be deposited on a top surface of a wafer 1000 including a two-dimensional array of dies 100.

Referring to step 920 and FIGS. 2C, 3A-3E, 5C, and 6A-6E, the wafer 1000 may be mounted on a wafer holder 20 using a wafer clamp assembly (120, 122, 130). The wafer clamp assembly (120, 122, 130) comprises a wafer clamp frame 120, a dielectric seal ring 122 interposed between the wafer clamp frame 120 and the wafer 1000, and a proximity mask 130 comprising a conductive material and having a cylindrical inner sidewall 131 that radially protrudes inward from an inner sidewall 121 of the wafer clamp frame 120 such that an annular region AR is provided between an annular backside surface 133 of the proximity mask 130 and a front side of the wafer 1000.

Referring to step 930 and FIGS. 3A-3E, 4A, 4B, 6A-6E, 7A, and 7B, an electroplating process may be performed in an electroplating bath 300 while the wafer holder 20 and the wafer 1000 are immersed in an electroplating solution 310 and while the proximity mask 130 is electrically biased such that such that electrical field within a predominant fraction of an entire volume of the annular region AR has a distribution of a tilt angle (α or β) relative to the axial direction AD that is greater than arctangent(0.1). The axial direction AD is parallel to a symmetry axis SA of the wafer 1000 that is perpendicular to a backside surface BS of the wafer 1000 and passes through a geometrical center GC of the wafer 1000.

The various embodiments of the present disclosure may be used to provide an electroplating apparatus that provides an electroplating process with enhanced thickness uniformity, and particularly an electroplating process with enhanced center-to-edge thickness uniformity. The electric field in the annular region AR is modified to provide a sufficient level of radial electrical field components. For example, the electrical field within a predominant fraction (i.e., at least 50%) of an entire volume of the annular region AR may have a distribution of a tilt angle (α or β) relative to the axial direction AD that is greater than arctangent(0.1) during the electroplating process, which provides a condition in which a conductive material layer (such as a metallic seed layer 52L) is present on a front side of the wafer 1000.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Each embodiment described using the term “comprises” also inherently discloses that the term “comprises” may be replaced with “consists essentially of” or with the term “consists of” in some embodiments, unless expressly disclosed otherwise herein. Whenever two or more elements are listed as alternatives in a same paragraph of in different paragraphs, a Markush group including a listing of the two or more elements may be also impliedly disclosed in some embodiments. Whenever the auxiliary verb “can” is used in this disclosure to describe formation of an element or performance of a processing step, an embodiment in which such an element or such a processing step is not performed is also expressly contemplated, provided that the resulting apparatus or device may provide an equivalent result. As such, the auxiliary verb “can” as applied to formation of an element or performance of a processing step should also be interpreted as “may” or as “may, or may not” whenever omission of formation of such an element or such a processing step is capable of providing the same result or equivalent results, the equivalent results including somewhat superior results and somewhat inferior results. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.