POLISHING PAD WITH HEAT DISSIPATION PATTERN

Description

BACKGROUND

Semiconductor or integrated circuit (IC) devices are constructed using complex fabrication processes that form a plurality of different layers on top of one another. Many of the layers are patterned using photolithography, in which a light sensitive photoresist material is selectively exposed to light. For example, photolithography is used to define back-end metallization layers that are formed on top of one another. To ensure that the metallization layers are formed with a good structural definition, the patterned light must be properly focused. To properly focus the pattered light, a workpiece must be substantially planar to avoid depth of focus problems.

Chemical mechanical polishing (CMP) is a widely used process by which both chemical and mechanical forces are used to globally planarize a semiconductor workpiece. The planarization prepares the workpiece for the formation of a subsequent layer. A typical CMP tool comprises a rotating platen covered by a polishing pad. A slurry distribution system is configured to provide a polishing mixture, having chemical and abrasive components, to the polishing pad. A workpiece is then brought into contact with the rotating polishing pad to planarize the workpiece. CMP is a favored process because it achieves global planarization across the entire wafer surface. The CMP process polishes and removes materials from the wafer, and works on multi-material surfaces. Furthermore, the CMP process avoids the use of hazardous gasses, and/or is usually a low-cost process.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with the standard practice in the industry, various features may not be drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 is a schematic view of a Chemical Mechanical Polishing (CMP) tool in accordance with some embodiments.

FIG. 2 is a perspective view of a polishing location in the CMP tool of FIG. 1 in accordance with some embodiments.

FIGS. 3-6 are cross-sectional schematic view of a wafer being transported to, and polished at, a polishing location in accordance with some embodiments.

FIG. 7 is a cross-sectional schematic view of a wafer, polishing pad, and platen at a polishing location in accordance with some embodiments.

FIGS. 8-13 are overhead schematic views of a portion of the upper surface of the polishing pad of FIG. 7 in accordance with some embodiments.

FIGS. 14-16 are generalized overhead schematic views of the upper surface of the polishing pad of FIG. 7 in accordance with some embodiments.

FIG. 17 is a perspective view of a wafer, polishing pad, and platen, and includes an expanded view of a portion of the polishing pad in accordance with some embodiments.

FIGS. 18-20 are perspective views of the nanostructure material of the polishing pad in accordance with some embodiments.

FIG. 21 is a flow chart illustrating a method in accordance with some embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the subject matter provided. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting.

For the sake of brevity, conventional techniques related to conventional semiconductor device fabrication may not be described in detail herein. Moreover, the various tasks and processes described herein may be incorporated into a more comprehensive procedure or process having additional functionality not described in detail herein. In particular, various processes in the fabrication of semiconductor devices are well-known and so, in the interest of brevity, many conventional processes will only be mentioned briefly herein or will be omitted entirely without providing the well-known process details. As will be readily apparent to those skilled in the art upon a complete reading of the disclosure, the structures disclosed herein may be employed with a variety of technologies, and may be incorporated into a variety of semiconductor devices and products. Further, it is noted that semiconductor device structures include a varying number of components and that single components shown in the illustrations may be representative of multiple components.

Furthermore, spatially relative terms, such as “over”, “overlying”, “above”, “upper”, “top”, “under”, “underlying”, “below”, “lower”, “bottom”, and the like, may be used herein for ease of description to describe one element's or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. When a spatially relative term, such as those listed above, is used to describe a first element with respect to a second element, the first element may be directly on the other element, or intervening elements or layers may be present. When an element or layer is referred to as being “on” another element or layer, it is directly on and in contact with the other element or layer.

In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

FIG. 1 is a schematic view of a Chemical Mechanical Polishing (CMP) device or tool 100. The tool 100 is configured for performing a CMP process on a wafer in a semiconductor manufacturing process. The CMP tool 100 may include a wafer transportation unit 110, a cleaning unit 120, and a polishing unit 130. Typically, the wafer transportation unit 110 transports a wafer to the polishing unit 130, where the wafer is polished. Thereafter, the wafer transportation unit 110 transports the wafer to the cleaning unit 120, wherein the wafer is cleaned.

As shown, a polishing unit 130 may include four polish locations or modules 200 where the unit 130 may perform a CMP operation on a wafer. For example, the polishing unit 200 may include a first main polishing module 201, a second main polishing module 202, a first chemical buff module 203, and a second chemical buff module 204. In certain embodiments, during operation of the polishing tool 100, a wafer may be processed in succession by each module 200. In certain embodiments, during operation of the polishing tool 100, a first wafer may be processed by the first main polishing module 201 and then by the first chemical buff module 203 while a second wafer may be processed by the second main polishing module 202, and then by the second chemical buff module 204. While FIG. 2 illustrates four polishing modules 200, any suitable number of polishing modules 200 may be employed.

FIG. 2 is a schematic view of a Chemical Mechanical Polishing (CMP) polishing module 200. The module 200 is configured for performing a CMP process on a wafer 15 in a semiconductor manufacturing process. As shown, the module 200 includes a polishing pad 20, a platen 30, a platen motor 40, and a wafer holder assembly 50, in accordance with some embodiments. The elements of the polishing module 200 can be added to or omitted, and the disclosure should not be limited by the embodiments.

The platen 30 is configured to receive and rotate the polishing pad 20 about a center axis 19. In some embodiments, the platen 30 is circular in shape. The diameter of the platen 30 lies in a range that is substantially larger than the diameter of a wafer 15 to be polished.

The platen motor 40 rotates the platen 30 about the axis 19. The platen motor 40 may be electrically connected to a control module in the CMP tool and may be actuated and operated by the control module.

In an embodiment, the polishing pad 20 is fixed onto the platen 30. The polishing pad 20 may be a consumable item used in a semiconductor wafer fabrication process. A polishing pad 20 may be a hard, incompressible pad or a soft pad. For oxide polishing, hard and stiffer pads are generally used to achieve planarity. Softer pads are generally used in other polishing processes to achieve improved uniformity and a smooth surface. Hard pad and soft pad components may also be combined in an arrangement for customized applications.

In certain embodiments, the polishing pad 20 may be formed by three-dimensional printing with desired portions formed from a material having a higher thermal conductivity and desired portions formed from material having a lower thermal conductivity, or formed with other desired attributes.

The wafer holder assembly 50 is used to support the wafer 15. In some embodiments, the wafer holder assembly 50 may include a shaft with a driving motor (not shown), a carrier head 52, and a retention ring 54. The driving motor may be configured to control rotational movement of the carrier head 52 and retention ring 54 about a rotation axis 56. The rotation axis 56 is different from the rotation axis 19. In some embodiments, the driving motor is an electric motor which converts electrical energy into mechanical energy for driving the rotation of the carrier head 52 and retention ring 54. In some embodiments, the carrier head 52 and retention ring 54 are driven to rotate about the rotation axis 56 by an external force (e.g., frictional force generated between the polishing pad 20 and the wafer 15).

Embodiments herein involve chemical mechanical polishing (CMP) processes and CMP tools such as the tool of FIGS. 1 and 2. CMP is a method of planarizing or flattening out a semiconductor wafer surface by polishing away a thin layer of wafer surface. Traditionally, CMP polishing pads include a single material and are formed by a molding fabrication process. However, it has been determined that such unitary molded CMP polishing pads may cause unstable removal rates of material, particularly for temperature sensitive material. In temperature sensitive materials, the removal rate is sensitive to the temperature. Some materials, particularly metal film such as tungsten or copper, are temperature sensitive such that the removal rate increases with an increase in temperature.

Increasing friction between a polishing pad and a wafer being polished leads to higher temperature at the interface of the wafer and the polishing pad surface. A higher temperature may cause a faster chemical reaction between the CMP slurry and the material being polished.

Friction may vary across the surface of the wafer due to the structures thereon. As a result, when removing a temperature sensitive material during a polishing process, varying rates of removal may be encountered over the wafer.

Variation in the removal rate of a temperature sensitive material due to localized temperature differences leads to worse within wafer (WiW) uniformity. In the short term, poor within wafer uniformity may be counteracted by controlling the downforce (DF) setting modification of the CMP tool. Specifically, the downforce on each zone of the wafer may by tuned and differ during a polishing process. However, an unhealthy downforce application may result in an increase in defects on the wafer over the longer term.

In addition, large removal rate variation leads to worse within zone (WiZ) uniformity. Polishing of semiconductor wafers may be analyzed by zones within the wafer surface. For example, a central zone may be circular and include the center of the wafer to a radius of 40 mm. A next zone may be annular and include the area from a radius of 40 mm to a radius of 70 mm. A next zone may be annular and include the area from a radius of 70 mm to a radius of 95 mm. A next zone may be annular and include the area from a radius of 95 mm to a radius of 122 mm. A next zone may be annular and include the area from a radius of 122 mm to a radius of 138 mm. A next zone may be annular and include the area from a radius of 138 mm to a radius of 145 mm. A last zone may be annular and include the area from a radius of 145 mm to a radius of 150 mm, or to the edge of the wafer.

Variation in the removal rate of a temperature sensitive material due to localized temperature differences leads to worse within zone (WiZ) uniformity. While downforce may be tuned to improve within wafer uniformity, within zone thickness uniformity is difficult to control by downforce or other tool settings. Further, within zone uniformity increases in importance when shrinking integrated circuit devices.

As semiconductor technology node advances to five nanometers and beyond, standards for within wafer and within zone thickness uniformity are increasingly stringent. Poor thickness uniformity across a wafer can lead to pattern failure, thus impacting chip yield and electrical characteristics.

Herein, embodiments are provided to mitigate material-induced temperature variation and to better control within wafer thickness uniformity and within zone thickness uniformity during CMP. Certain embodiments use a combination of polishing pad materials to material-induced temperature variation. Certain embodiments use a polishing pad layout designs to achieve uniform temperature distribution across whole wafer. For example, certain embodiments include a polishing pad formed with materials having different thermal conductivities in an arrangement to form a polishing surface of the polishing pad with a desired heat dissipation pattern.

As a result, certain embodiments provide more uniform heat transfer on the polishing pad, allow for healthier down force settings on the CMP tool and lower defect risks, increase within wafer uniformity of planarized wafers, increase within zone uniformity of planarized wafers, and/or increase uniformity between planarized wafers, i.e., wafer-to-wafer (WtW) uniformity. With increased within wafer thickness uniformity and higher polish performance stability, chip yield and integrated circuit device performance may be sharply improved.

Certain embodiments provide a CMP polishing pad with pixel-level material and structural designs to improve heat distribution during polishing, thus increasing within-wafer (WiW) and within-zone (WiZ) uniformity for yield and electrical property improvement. Certain embodiments provide a temperature-controlled three-dimensional (3D) printed polishing pad.

Referring to FIGS. 3-6, the structure of the wafer holder assembly 50 is shown more clearly. As shown, the carrier head 52 has a bottom surface 61 and an outer perimeter 62. The retention ring 54 has an annular shape and is mounted on the outer perimeter 62 of the carrier head 52. Further, the retention ring 54 has an inner surface 65, such as a cylindrical surface 65, and extends downward to a terminal surface 66 at a distance from the bottom surface 61 of the carrier head 52. As a result, a recess or pocket 67 is defined by the wafer holder assembly 50, below the bottom surface 61 of the head 52, above the terminal surface 66 of the retention ring 54, and inside of the inner surface 65 of the retention ring 54.

While FIGS. 3-6 illustrate the retention ring 54 located outside the periphery of the carrier head 52, other designs are envisioned. For example, the carrier head 52 may be formed with an inner cylindrical wall surface and the retention ring 54 may be positioned inside of such wall surface. Further, a retention ring cushion may be positioned between the retention ring 54 and the carrier head 52 to cushion movement therebetween.

As further shown, the wafer holder assembly 50 may include a flexible membrane 58. Flexible membrane 58 is used to provide a flat surface for securing a wafer 15 to the carrier head 52.

Though not shown, the wafer holder assembly 50 may further include a port or ports to the pocket 67 for applying a positive pressure to an internal surface of flexible membrane 58 in order to help maintain a flat surface for supporting wafer 15 and to evenly distribute pressure applied to the wafer 15.

Further, though not shown, the wafer holder assembly 50 may include a port or ports for applying a negative pressure to an external surface of flexible membrane 58 in order to hold the wafer 15 with the wafer holder assembly 50. When the wafer 15 is to be released from the wafer holder assembly 50, such as following a polishing process, the negative pressure may be released or a positive pressure may be applied.

Thus, the wafer holder assembly 50 is configured pick up a wafer 15, transport the wafer 15, and hold the wafer 15 against polishing pad 20. Carrier head 52 may be capable of moving in a direction perpendicular to a polishing surface of polishing pad 20 in order to adjust a pressure applied to wafer 15 during the polishing process. A membrane support structure may be positioned in the pocket 67 to provide support for membrane 58 during the polishing process. Retention ring 54 is used to reduce lateral movement of wafer 15 during the polishing process. In order to reduce lateral movement of wafer 15, retention ring 54 may be pressed against polishing pad 20.

In FIG. 3, the wafer holder assembly 50 is moved in the direction of arrow 71 toward wafer 15. As shown wafer 15 is supported by a wafer tray 75. The retention ring 54 of the wafer holder assembly 50 may be moved into contact with the wafer tray 75. Then, the membrane 58 may be operated to contact the wafer 15 and draw the wafer 15 against the membrane 58, such as through the selective application of positive and negative pressure.

In FIG. 4, the wafer holder assembly 50 is lifted in the direction of arrow 72. As shown, the wafer 15 is removed from the wafer tray 75 and is carried by the wafer holder assembly 50. With cross-reference to FIG. 2, the wafer holder assembly 50 may carry the wafer 15 to a polishing pad 20.

In FIG. 5, the wafer holder assembly 50 is moved in the direction of arrow 73 toward the polishing pad 20, and may be moved into contact with the polishing pad 20.

In FIG. 6, the wafer holder assembly 50 is in contact with the polishing pad 20 and may be rotated about axis 56, such as in the direction of arrow 74, during a polishing process. As shown, the retention ring 54 may contact the polishing pad 20 during the polishing process. Further, the membrane 58 and/or carrier head 52 may impart a desired pressure to the wafer 15 against the polishing pad 20.

Referring now to FIG. 7, a rotatable structure 700 including a polishing pad 20 and platen 30 is illustrated while supporting a wafer 15. The polishing pad 20 includes a polishing surface 21 and an opposite surface 22 that is located on and supported by the platen 30. Likewise, the platen 30 includes a top surface 31, which supports the polishing pad 20, and an opposite surface 32.

In some embodiments, the polishing pad 20 is formed from pixels or grains 90 that are fused during a three-dimensional printing process. Through use of three-dimensional printing, the thermal conductivity, i.e., K value, and other properties of the polishing pad 20 may be controlled at a pixel level. Specifically each grain or material fraction can be manufactured by three-dimensional printing technology providing for pixel-level precision control.

Each grain may independently have a thermal conductivity K value of at least 0.01, at least 0.03, at least 0.05, at least 0.08, at least 0.1, at least 0.12, at least 0.15, at least 0.2, at least 0.25, at least 0.3, at least 0.35, at least 0.4, at least 0.45, at least 0.5, at least 0.6, at least 0.7, at least 0.8, at least 0.9, at least 1.0, at least 1.2, at least 1.5, at least 1.8, at least 2.0, at least 2.2, at least 2.5, at least 2.8, at least 3.0, at least 3.2, at least 3.5, at least 3.8, at least 4, at least 5, at least 6, at least 7, at least 8, at least 9, at least 10, at least 12, at least 15, at least 20, at least 25, at least 30, at least 35, at least 40, or at least 45 W/mK. Also, each grain may independently have a thermal conductivity K value of at most 0.02, at most 0.03, at most 0.05, at most 0.08, at most 0.1, at most 0.12, at most 0.15, at most 0.2, at most 0.25, at most 0.3, at most 0.35, at most 0.4, at most 0.45, at most 0.5, at most 0.6, at most 0.7, at most 0.8, at most 0.9, at most 1.0, at most 1.2, at most 1.5, at most 1.8, at most 2.0, at most 2.2, at most 2.5, at most 2.8, at most 3.0, at most 3.2, at most 3.5, at most 3.8, at most 4, at most 5, at most 6, at most 7, at most 8, at most 9, at most 10, at most 12, at most 15, at most 20, at most 25, at most 30, at most 35, at most 40, at most 45, or at most 50 W/mK.

For example, the grains 90 may include material grains 91 having a high thermal conductivity, material grains 92 having a low or lower thermal conductivity, and, optionally, material grains 93 having a low or lowest thermal conductivity. In certain embodiments the K value of the thermal conductivity of the grains 90 at 25° C. may be from 0.01 to 50 W/mK. Herein, the grains 91 are formed from a first material, the grains 92 are formed from a second material, and the grains 93 are formed from a third material. The first material has a greater or higher thermal conductivity than the second material, and the second material has a greater or higher thermal conductivity than the third material.

For example, the first material may be an acrylic and have a thermal conductivity K value of 0.2 W/mK or a polyimide and have a thermal conductivity K value of 0.12 W/mK; the second material may be a polyimide and have a thermal conductivity K value of 0.12 W/mK or a polyester and have a thermal conductivity K value of 0.05 W/mK; and the third material may be a polyester and have a thermal conductivity K value of 0.05 W/mK or a polyurethane and have a thermal conductivity K value of 0.03 W/mK.

The grains 90 may comprise materials suitable for three-dimensional printing, such as polyimides, acrylics, polyesters, polyurethanes and other materials. While three different materials are illustrated and described, it is contemplated that two, three, or more than three different materials are used to form the polishing pad. In certain embodiments, the material grains 93 have no material and act as pores or voids, i.e., the material grain 93 location is vacant.

In certain embodiments, the grains 90 are arranged to form a desired heat dissipation pattern. The pattern may extend laterally, such as along the surface 21. In certain embodiments, the pattern extends vertically, such as into the pad 20. The pattern may include conductive paths, defined by higher thermal conductive material, along which heat may be dissipated from a hot region on the surface. Further, the pattern may include insulative barriers, defined by lower thermal conductive material, at which heat is not as easily conducted.

FIGS. 8-13 are overhead views of a portion of the upper surface 21 of the polishing pad 20 of FIG. 7 according to different embodiments. As shown in FIGS. 8-13, the pixels or grains 90 may be formed with different shapes. For example, in FIG. 8, each grain 90 has a circular cross-section and may be a sphere, spheroid, or cylindrical. As shown, grains 91 having a higher thermal conductivity and grains 92 having a lower thermal conductivity are arranged in a desired patterns. Pores or voids 95 are formed between adjacent grains 90 that do not contact one another continuously.

In FIG. 9, each grain 90 has a square cross-section and may be a cuboid. As shown, grains 91 having a higher thermal conductivity and grains 92 having a lower thermal conductivity are arranged in a desired patterns. As square grains 91 and 92 align with one another without forming voids therebetween, pores or voids 95 may be formed at desired locations by not forming a grain 90 at that location.

In FIG. 10, each grain 90 has a rectangular cross-section and may be a cuboid. As shown, grains 91 having a higher thermal conductivity and grains 92 having a lower thermal conductivity are arranged in a desired patterns. As rectangular grains 91 and 92 align with one another without forming voids therebetween, pores or voids 95 may be formed at desired locations by not forming a grain 90 at that location.

In FIG. 11, each grain 90 has a triangular cross-section and may be a triangular prism or pyramid. As shown, grains 91 having a higher thermal conductivity and grains 92 having a lower thermal conductivity are arranged in a desired patterns. As triangular grains 91 and 92 align with one another without forming voids therebetween, pores or voids 95 may be formed at desired locations by not forming a grain 90 at that location.

In FIG. 12, each grain 90 has a pentagonal cross-section and may be a pentagonal prism. As shown, grains 91 having a higher thermal conductivity and grains 92 having a lower thermal conductivity are arranged in a desired patterns. Pores or voids 95 are formed between adjacent grains 90 that do not contact one another continuously.

In FIG. 13, each grain 90 has a hexagonal cross-section and may be a hexagonal prism. As shown, grains 91 having a higher thermal conductivity and grains 92 having a lower thermal conductivity are arranged in a desired patterns. As hexagonal grains 91 and 92 align with one another without forming voids therebetween, pores or voids 95 may be formed at desired locations by not forming a grain 90 at that location.

FIGS. 14-16 are overhead views schematic views of the upper surface 21 of the polishing pad 20 of FIG. 7 according to different embodiments. In FIGS. 14-16, the upper surface 21 includes different regions which are provided with different desired levels of thermal conductivity. The regions may be centered about the axis of rotation of the polishing pad 20. In certain embodiments, grains 90 are distributed to form a desired pad region design as shown in FIGS. 14-16.

In FIGS. 14-16, the polishing surface 21 has a circular periphery centered on an axis, and the polishing surface 21 is formed with radially-arranged regions having different desired thermal conductivities. For example, each region may have an independently selected radial width. For example, each radial width may be from 1 micrometer to 40 millimeters, such as from 1 to 400 micrometers. Further, each region may independently have a thermal conductivity K value of at least 0.01, at least 0.03, at least 0.05, at least 0.08, at least 0.1, at least 0.12, at least 0.15, at least 0.2, at least 0.25, at least 0.3, at least 0.35, at least 0.4, at least 0.45, at least 0.5, at least 0.6, at least 0.7, at least 0.8, at least 0.9, at least 1.0, at least 1.2, at least 1.5, at least 1.8, at least 2.0, at least 2.2, at least 2.5, at least 2.8, at least 3.0, at least 3.2, at least 3.5, at least 3.8, at least 4, at least 5, at least 6, at least 7, at least 8, at least 9, at least 10, at least 12, at least 15, at least 20, at least 25, at least 30, at least 35, at least 40, or at least 45 W/mK. Also, each region may independently have a thermal conductivity K value of at most 0.02, at most 0.03, at most 0.05, at most 0.08, at most 0.1, at most 0.12, at most 0.15, at most 0.2, at most 0.25, at most 0.3, at most 0.35, at most 0.4, at most 0.45, at most 0.5, at most 0.6, at most 0.7, at most 0.8, at most 0.9, at most 1.0, at most 1.2, at most 1.5, at most 1.8, at most 2.0, at most 2.2, at most 2.5, at most 2.8, at most 3.0, at most 3.2, at most 3.5, at most 3.8, at most 4, at most 5, at most 6, at most 7, at most 8, at most 9, at most 10, at most 12, at most 15, at most 20, at most 25, at most 30, at most 35, at most 40, at most 45, or at most 50 W/mK.

In FIG. 14, the upper surface 21 of the polishing pad 20 is provided with an inner low K design. Specifically, the upper surface 21 has a central inner region 81 that is formed with a low K material, i.e., a lower thermal conductivity than a radially outer region.

The inner surrounding region 82 may be formed from a material having an increased thermal conductivity, i.e., a thermal conductivity greater than the thermal conductivity of the central region 81.

The next surrounding region 83 may be formed from a material having an intermediate thermal conductivity, i.e., a thermal conductivity greater than the thermal conductivity of region 82.

An outermost surrounding region 84 may be formed from a material having an increased thermal conductivity, i.e., a thermal conductivity greater than the thermal conductivity of region 83, such as a high K material.

In FIG. 15, the upper surface 21 of the polishing pad 20 is provided with an inner high K design. Specifically, the upper surface 21 has a central region 81 that is formed with a high K material, i.e., a higher thermal conductivity than a radially outer region.

The inner surrounding region 82 may be formed from a material having a decreased thermal conductivity, i.e., a thermal conductivity less than the thermal conductivity of the central region 81.

The next surrounding region 83 may be formed from a material having an intermediate thermal conductivity, i.e., a thermal conductivity less than the thermal conductivity of region 82.

The outermost region 84 may be formed from a material having a decreased thermal conductivity, i.e., a thermal conductivity less than the thermal conductivity of region 83, such as a low K material.

FIG. 16 illustrates another embodiment in which the upper surface 21 of the polishing pad 20 is provided with a higher number of regions. For example, a series of regions are formed from the axis to the circular periphery, a central inner region may be formed with a lower thermal conductivity than a radially outer region and a peripheral region may be formed with a lower thermal conductivity than the radially outer region.

In FIG. 16, a central region 81 is formed with a low K material. Surrounding region 82 is formed with a thermal conductivity greater than central region 81. Surrounding region 83 is formed with a high K material having a thermal conductivity greater than region 82. Then, the pattern repeats with surrounding region 84 being formed with a low K material, surrounding region 85 formed with a thermal conductivity greater than region 84, and outermost region 86 formed with a high K material having a thermal conductivity greater than region 85.

FIG. 17 provides a schematic perspective view of a polishing pad and with a focused view of a portion of the polishing pad. As shown, the polishing pad 20 has a thickness T from the bottom surface 22 to the top surface 21. Further, the polishing pad 20 is formed with a nanostructure material 70 dispersed in a non-nanostructure material 60 extending from the bottom surface 22 to the top surface 21, and includes the polishing surface 21 and a sub-surface portion below the polishing surface. The sub-surface portion is formed from the nanostructure material 70. In the illustrated embodiment, the nanostructure material 70 comprises nanospheres. In other embodiments, the nanostructure material 70 comprises nanocubes or nano dendric structures. In certain embodiments, the nanostructure material 70 is a relatively high thermal conductivity, i.e., high K, material to form a conductive path, while the non-nanostructure material 60 includes grains of high K and/or low K materials as described above. In certain embodiments, the nanostructure has a higher K value than the non-nanostructure material. In certain embodiments, the nanostructure material 70 is a metal. In certain embodiments, the nanostructure material 70 is selected from silver (Ag), copper (Cu), gold (Au), aluminum (Al), sodium (Na), molybdenum (Mo), tungsten (W), nickel (Ni), iron (Fe), platinum (Pt), tin (Sn), and/or lead (Pb).

In certain embodiments, the nanostructure material 70 and non-nanostructure material 60 are formed by three-dimensional printing and can be formed in any desired pattern in the lateral (X), longitudinal (Y), and vertical (Z) dimensions.

FIGS. 18-20 illustrate the various shapes of the nanostructure material. Specifically, FIG. 18 illustrates the nanostructure material 70 including a sphere 76, FIG. 19 illustrates the nanostructure material including a cube 77, and FIG. 20 illustrates the nanostructure material including a nano dendric structure 78. While FIGS. 18-20 illustrate certain shapes, embodiments herein are not limited to the shapes of FIGS. 18-20.

In certain embodiments, the polishing pad 20 is formed with a desired arrangement of nanostructure materials 70 to provide the desired thermal dissipation path. In certain embodiments, the nanostructure material 70 may include more than one shape.

Cross-referencing FIGS. 7-20, it may be seen that a polishing pad may be formed with a desired grain or pixel shape (FIGS. 8-13), a desired pad region design (FIGS. 14-16), and a desired nanostructure (FIGS. 18-20). While not limited to the illustrated embodiments, as illustrated there are different pixel shapes, three different pad region designs, and three different nanostructures. Thus, a polishing pad may be formed with a combination of features including circle pixel shape/inner low K region design/nanosphere nanostructure; circle pixel shape/inner low K region design/nanocube nanostructure; circle pixel shape/inner low K region design/nano dendric structure nanostructure; circle pixel shape/inner high K region design/nanosphere nanostructure; circle pixel shape/inner high K region design/nanocube nanostructure; circle pixel shape/inner high K region design/nano dendric structure nanostructure; circle pixel shape/mixed K region design/nanosphere nanostructure; circle pixel shape/mixed K region design/nanocube nanostructure; circle pixel shape/mixed K region design/nano dendric structure nanostructure; square pixel shape/inner low K region design/nanosphere nanostructure; square pixel shape/inner low K region design/nanocube nanostructure; square pixel shape/inner low K region design/nano dendric structure nanostructure; square pixel shape/inner high K region design/nanosphere nanostructure; square pixel shape/inner high K region design/nanocube nanostructure; square pixel shape/inner high K region design/nano dendric structure nanostructure; square pixel shape/mixed K region design/nanosphere nanostructure; square pixel shape/mixed K region design/nanocube nanostructure; square pixel shape/mixed K region design/nano dendric structure nanostructure; rectangular pixel shape/inner low K region design/nanosphere nanostructure; rectangular pixel shape/inner low K region design/nanocube nanostructure; rectangular pixel shape/inner low K region design/nano dendric structure nanostructure; rectangular pixel shape/inner high K region design/nanosphere nanostructure; rectangular pixel shape/inner high K region design/nanocube nanostructure; rectangular pixel shape/inner high K region design/nano dendric structure nanostructure; rectangular pixel shape/mixed K region design/nanosphere nanostructure; rectangular pixel shape/mixed K region design/nanocube nanostructure; rectangular pixel shape/mixed K region design/nano dendric structure nanostructure; triangular pixel shape/inner low K region design/nanosphere nanostructure; triangular pixel shape/inner low K region design/nanocube nanostructure; triangular pixel shape/inner low K region design/nano dendric structure nanostructure; triangular pixel shape/inner high K region design/nanosphere nanostructure; triangular pixel shape/inner high K region design/nanocube nanostructure; triangular pixel shape/inner high K region design/nano dendric structure nanostructure; triangular pixel shape/mixed K region design/nanosphere nanostructure; triangular pixel shape/mixed K region design/nanocube nanostructure; triangular pixel shape/mixed K region design/nano dendric structure nanostructure; pentagonal pixel shape/inner low K region design/nanosphere nanostructure; pentagonal pixel shape/inner low K region design/nanocube nanostructure; pentagonal pixel shape/inner low K region design/nano dendric structure nanostructure; pentagonal pixel shape/inner high K region design/nanosphere nanostructure; pentagonal pixel shape/inner high K region design/nanocube nanostructure; pentagonal pixel shape/inner high K region design/nano dendric structure nanostructure; pentagonal pixel shape/mixed K region design/nanosphere nanostructure; pentagonal pixel shape/mixed K region design/nanocube nanostructure; pentagonal pixel shape/mixed K region design/nano dendric structure nanostructure; hexagonal pixel shape/inner low K region design/nanosphere nanostructure; hexagonal pixel shape/inner low K region design/nanocube nanostructure; hexagonal pixel shape/inner low K region design/nano dendric structure nanostructure; hexagonal pixel shape/inner high K region design/nanosphere nanostructure; hexagonal pixel shape/inner high K region design/nanocube nanostructure; hexagonal pixel shape/inner high K region design/nano dendric structure nanostructure; hexagonal pixel shape/mixed K region design/nanosphere nanostructure; hexagonal pixel shape/mixed K region design/nanocube nanostructure; and hexagonal pixel shape/mixed K region design/nano dendric structure nanostructure.

Referring to FIG. 21, a flow chart of a method 900 is illustrated. Cross-referencing FIG. 21 with FIGS. 1-20, method 900 includes, at operation S11, providing a design layout for a wafer. The design layout may include a dense region including densely arranged temperature sensitive material and an isolation region including less temperature sensitive material. The design layout may be of an existing wafer, or of a designed wafer. For example, a process module may be used to model a design layout of a wafer. As used herein, the term “process module” refers to any hardware, software, firmware, electronic control unit or component, processing logic, and/or processor device, individually or in any combination, including without limitation: application specific integrated circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group) and memory that executes one or more software or firmware programs, a combinational logic circuit, and/or other suitable components that provide the described functionality. An embodiment of the present disclosure may employ various integrated circuit components, e.g., memory elements, digital signal processing elements, logic elements, look-up tables, or the like, which may conduct a variety of functions under the control of one or more microprocessors or other control devices.

At operation S12, method 900 includes simulating polishing of a wafer with the design layout. For example, a process module may be used to model polishing of the wafer. In certain embodiments, simulating polishing of the wafer includes determining heat distribution during polishing. In certain embodiments, simulating polishing of the wafer includes determining the removal rate variation of the wafer during polishing.

Method 900 may continue at operation S13 with designing a heat dissipation pattern for a polishing pad to reduce removal rate variation of the wafer during polishing. For example, a process module may be used to design the heat dissipation pattern for the polishing pad. In certain embodiments, the heat dissipation pattern is designed based on what areas of the wafer are more temperature sensitive, i.e., what areas of the wafer experience high temperatures being polished. For example, the pattern is designed such that pad areas with higher K value grains or higher K value regions correspond to areas of the wafer that are heat sensitive, i.e., that experience high temperatures when being polished. Likewise, pad areas with lower K value grains or lower K value regions correspond to areas of the wafer that are less heat sensitive, i.e., that do not experience high temperatures when being polished.

At operation S14, method 900 includes manufacturing the polishing pad with the heat dissipation pattern.

In certain embodiments, manufacturing the polishing pad with the heat dissipation pattern includes manufacturing the polishing pad from a first material with a first thermal conductivity and a second material with a second thermal conductivity less than the first thermal conductivity.

In certain embodiments, manufacturing the polishing pad with the heat dissipation pattern includes fusing first grains formed from a first material with a first thermal conductivity and second grains formed from a second material with a second thermal conductivity less than the first thermal conductivity in an arrangement.

In certain embodiments, manufacturing the polishing pad with the heat dissipation pattern includes performing a three-dimensional printing process, such as with a first material formed from a selected grain shape with a relatively high thermal conductivity and a second material with a relatively low thermal conductivity.

Operations S11 through S14 may be considered to represent a method for manufacturing a polishing pad.

Method 900 may continue at operation S21 with providing a polishing tool 100 including the rotatable polishing pad 20 manufactured at operation S14.

Further, method 900 includes contacting an object 15 with the surface 21 of the polishing pad 20 at operation S22. For example, a wafer 15 may be picked up and moved into contact with the polishing pad 20 as illustrated in FIGS. 3-5.

Method 900 also includes spinning the polishing pad 20 at operation S23, and as indicated in FIG. 2.

In some embodiments, method 900 includes rotating the object 15 at operation S24, as further indicated in FIGS. 2 and 6.

Further, method 900 may include introducing a polishing agent to the surface 21 at operation S25.

Also, method 900 includes dissipating heat from the polishing surface through the heat dissipation pattern at operation S26. In some embodiments, operations S23, S24, S25 and S26 may be performed simultaneously.

Also, method 900 may include removing a waste stream from the polishing surface 21 at operation S27. The removal of the waste stream may be selectively performed, such as to remove a first polishing agent before a second polishing agent is introduced or continuously with the application of polishing agents.

Method 900 may further include, at operation S28, controlling the rate of delivering selected polishing agents and removing waste streams to optimize polishing of the wafer 15.

When the desired polished surface is achieved on the object, the method 900 may include removing the object from the polishing pad at operation S29.

Operations S21 through S29 may be considered to represent a method for polishing a wafer.

As described herein, embodiments provide for improved heat transfer away from hot regions and/or away from temperature sensitive material on a wafer at the interface of a polishing pad and the wafer. Embodiments may use grains or pixels of selected material having desired thermal conductivities in an arrangement to provide a heat dissipation pattern optimized and dedicated for use with the selected wafer design layout. Embodiments may use nanostructures with a selected thermal conductivity to provide uniform heat transfer to dissipate heat. In certain embodiments, the heat dissipation pattern minimizes temperature variability at the wafer surface during polishing. As a result, within wafer thickness uniformity and within zone thickness uniformity are improved.

As described herein, a polishing pad, tool and method for polishing wafers are provided with better control of within wafer and within zone thickness uniformity and a reduction in CMP-induced defects.

Through the use of the polishing pad, tool and method described herein, a CMP process may be provided with healthier downforce settings, increased within wafer thickness uniformity, increased within zone thickness uniformity, and a reduction in CMP-induced defectivity. With more uniform within wafer thickness uniformity and within zone thickness uniformity, chip yield and IC device performance are sharply improved.

In an embodiment, a polishing pad for polishing a semiconductor wafer, the polishing pad including first grains formed from a first material with a first thermal conductivity; and second grains formed from a second material with a second thermal conductivity less than the first thermal conductivity. The first grains and second grains are arranged, such as fused together in an arrangement, to form a polishing surface of the polishing pad to provide the polishing surface with a desired heat dissipation pattern.

In certain embodiments of the polishing pad, the polishing pad is formed with voids located on the polishing surface.

In certain embodiments of the polishing pad, at the polishing surface the grains have a surface shape selected from circle, square, rectangle, triangle, pentagon, and hexagon.

In certain embodiments of the polishing pad, the polishing surface has a circular periphery centered on an axis, and wherein the polishing surface is formed with radially-arranged regions having different desired thermal conductivities.

In certain embodiments of the polishing pad, a central inner region is formed with a lower thermal conductivity than a radially outer region.

In certain embodiments of the polishing pad, a central inner region is formed with a higher thermal conductivity than a radially outer region.

In certain embodiments of the polishing pad, a series of regions are formed from the axis to the circular periphery, wherein a central inner region is formed with a lower thermal conductivity than a radially outer region and wherein a peripheral region is formed with a lower thermal conductivity than the radially outer region.

In certain embodiments of the polishing pad, the polishing pad includes a sub-surface portion formed from a nanostructure material configured to transfer heat from the polishing surface.

In certain embodiments of the polishing pad, the nanostructure material includes nanospheres, nanocubes, or nano dendric structures.

In another embodiment, a method for manufacturing a polishing pad includes providing a wafer layout design for a wafer; simulating polishing of the wafer to determine heat distribution during polishing; designing a heat dissipation pattern for a polishing pad to reduce removal rate variation of the wafer during polishing; and manufacturing the polishing pad with the heat dissipation pattern.

In certain embodiments of the method, simulating polishing of the wafer includes determining the removal rate variation of the wafer during polishing.

In certain embodiments of the method, manufacturing the polishing pad with the heat dissipation pattern includes manufacturing the polishing pad from a first material with a first thermal conductivity and a second material with a second thermal conductivity less than the first thermal conductivity.

In certain embodiments of the method, manufacturing the polishing pad with the heat dissipation pattern includes fusing first grains formed from a first material with a first thermal conductivity and second grains formed from a second material with a second thermal conductivity less than the first thermal conductivity in an arrangement.

In certain embodiments of the method, manufacturing the polishing pad with the heat dissipation pattern includes performing a three-dimensional printing process.

In certain embodiments of the method, the heat dissipation pattern is formed by a first material formed from a selected grain shape.

In another embodiment, a method for polishing includes contacting an object to a polishing surface of a polishing pad, wherein the polishing surface has a desired heat dissipation pattern formed by a first material with a first thermal conductivity and a second material with a second thermal conductivity less than the first thermal conductivity; rotating the object and/or the pad; and dissipating heat from the polishing surface through the desired heat dissipation pattern.

In certain embodiments of the method, the polishing pad is formed with voids located on the polishing surface.

In certain embodiments of the method, the polishing surface has a circular periphery centered on an axis, and wherein the polishing surface is formed with radially-arranged regions having different desired thermal conductivities.

In certain embodiments of the method, the polishing pad includes a sub-surface portion formed from a nanostructure material configured to transfer heat from the polishing surface.

In certain embodiments of the method, the nanostructure material includes nanospheres, nanocubes, and/or nano dendric structures.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.