RETAINING RING WEAR CHARACTERIZATION FOR CMP PROCESSES

Description

FIELD

Descriptions are generally related to semiconductor processing, and more particular descriptions are related to characterizing wear on a retaining ring for chemical mechanical planarization processes.

BACKGROUND

Semiconductor chips are central to intelligent devices and systems, such as personal computers, laptops, tablets, phones, servers, and other consumer and industrial products and systems. Manufacturing semiconductor chips presents a number of challenges and these challenges are amplified as devices become smaller and performance demands increase. Challenges include, for example, unwanted material interactions, precision and scaling requirements, power delivery requirements, limited failure tolerance, and material and manufacturing costs.

Chemical mechanical polish (or planarization (CMP) is one process used in manufacturing semiconductor chips. Semiconductor chips are manufactured in parallel on a wafer and then diced apart to create the individual chips (or dies). CMP can employ mechanical abrasion and/or chemical oxidation to remove unwanted layers and/or material from the surface of a wafer. For example, after a deposition process that places material into trenches on a wafer surface, CMP can be used to remove the deposited material from the wafer surface while leaving the deposited material in the trenches. CMP can also be used to thin or planarize a wafer surface.

BRIEF DESCRIPTION OF THE DRAWINGS

The figures are provided to aid in understanding the disclosure. The figures can include diagrams and illustrations of examples of structures, assemblies, data, methods, and systems. For ease of explanation and understanding, these structures, assemblies, data, methods, and systems, the figures are not an exhaustively detailed description. The figures therefore should not be understood to depict the entire metes and bounds of structures, assemblies, data, methods, and systems possible without departing from the scope of the disclosure. Additionally, features are not necessarily illustrated relatively to scale due in part to the small sizes of some features and the desire for clarity of explanation in the figures.

FIG. 1 illustrates a chemical mechanical planarization process.

FIGS. 2A-2B shows a system for determining two dimensional (2D) and three dimensional (3D) wear profiles for semiconductor wafer retaining rings.

FIGS. 3A-3B illustrate 2D and 3D profiles, respectively, of an exemplary semiconductor wafer retaining ring.

FIG. 4 provides a method for managing wafer retaining rings used in chemical mechanical planarization processes.

FIG. 5 provides an example of a compute system.

Descriptions of certain details and implementations follow, including non-limiting descriptions of the figures, which depict some examples and implementations.

DETAILED DESCRIPTION

References to one or more examples are to be understood as describing a particular feature, structure, or characteristic included in at least one implementation. The phrases “one example” or “an example” are not necessarily all referring to the same example or embodiment. Any aspect described herein can potentially be combined with any other aspect or similar aspect described herein, regardless of whether the aspects are described with respect to the same figure or element.

The words “connected” and/or “coupled” can indicate that two or more elements are in direct physical or electrical contact with each other. The term “coupled,” however, can also mean that two or more elements are not in direct contact with each other and are instead separated by one or more elements but they may still co-operate or interact with each other, for example, physically, magnetically, optically, or electrically.

The words “first,” “second,” and the like, do not indicate order, quantity, or importance, but rather are used to distinguish one element from another. The words “a” and “an” herein do not indicate a limitation of quantity, but rather denote the presence of at least one of the referenced items. The terms “follow” or “after” can indicate immediately following or following some other event or events. Other sequences of operations can also be performed according to alternative embodiments. Furthermore, additional operations may be added or removed depending on the application.

Disjunctive language such as the phrase “at least one of X, Y, or Z,” is used in general to indicate that an element or feature, may be either X, Y, or Z, or any combination thereof (e.g., X, Y, and/or Z). Thus, this disjunctive language should be understood not to imply that certain embodiments require at least one of X, at least one of Y, or at least one of Z to each be present.

Flow diagrams as illustrated herein provide examples of sequences of various process actions. The flow diagrams can indicate operations to be executed by a software or firmware routine, as well as by physical operations. Physical operations can be performed by semiconductor processing and/or testing equipment, including computer systems that run testing protocols and operate aspects of testing equipment and systems. Although shown in a particular sequence or order, unless otherwise specified, the order of the actions can be modified. Thus, the illustrated diagrams should be understood as examples. The processes can be performed in a different order, and some actions can be performed in parallel. Additionally, one or more actions can be omitted and not all implementations may necessarily perform all actions.

Various components described can be a means for performing the operations or functions described. Components described can include software, hardware, or a combination of these. Some components can be implemented as software modules, hardware modules, special-purpose hardware (for example, application specific hardware, application specific integrated circuits (ASICs), and digital signal processors (DSPs)), embedded controllers, and/or hardwired circuitry. Other components can be semiconductor processing and/or testing equipment that is able to perform physical operations such as, for example, lithography, probing, material deposition (for example, chemical vapor deposition, atomic layer deposition, physical vapor deposition, electrodeposition, and/or sputtering), chemical mechanical planarization (CMP), and etching.

To the extent various computer operations or functions are described herein, they can be described or defined as software code, instructions, configuration, and/or data. The software content can be provided via an article of manufacture with the content stored thereon, or via a method of operating a communication interface to send data via the communication interface. A machine-readable storage medium can cause a machine to perform the functions or operations described. A machine-readable storage medium includes any mechanism that stores information in a tangible form accessible by a machine (e.g., compute device), such as recordable/non-recordable media (e.g., read only memory (ROM), random access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices). Instructions can be stored on the machine-readable storage medium in a non-transitory form. A communication interface includes any mechanism that interfaces to, for example, a hardwired, wireless, or optical medium to communicate to another device, such as, for example, a memory bus interface, a processor bus interface, an Internet connection, a disk controller.

Terms such as chip, die, IC (integrated circuit) chip, IC die, microelectronic chip, microelectronic die, semiconductor die, semiconductor device, and/or semiconductor chip are interchangeable and refer to a device comprising integrated circuits that can be formed in part from semiconductor materials.

Semiconductor chip manufacturing processes are sometimes divided into front end of the line (FEOL) processes and back end of the line (BEOL) processes. Electronic circuits and active and passive devices within the chip, such as for example, transistors, capacitors, resistors, and/or memory cells, are manufactured in what can be referred to as FEOL processes. Memory cells include, for example, electronic circuits for random access memory (RAM), such as static RAM (sRAM), dynamic RAM (DRAM), read only memory (ROM), non-volatile memory, and/or flash memory. FEOL processes can be, for example, complementary metal-oxide semiconductor (CMOS) processes. BEOL processes include metallization of the chip where interconnects are formed in layers and the feature size of the interconnect increases in layers nearer the surface of the semiconductor chip. Interconnects in, for example, semiconductor chips that are integrated into heterogeneous packages (such as, for example, packages that include memory and logic chips), can also include through silicon vias (TSVs) that transverse the semiconductor chip device region. Semiconductor devices that have TSVs can blur distinctions between BEOL and FEOL processes.

Semiconductor chip interconnects can be created by forming a trench or though-layer via by etching a trench or via structure into a dielectric layer and filling the trench or via with metal. Dielectric layers can comprise, for example, low-κ dielectrics, SiO₂, silicon nitride (SiN), silicon carbide (SiC), and/or silicon carbonitride (SiCN). Low-κ dielectrics include for example, fluorine-doped SiO₂, carbon-doped SiO₂, porous SiO₂, porous carbon-doped SiO₂, combinations for the foregoing, and also these materials with gas-filled gaps or bubbles. Dielectric layers that include conductive features can be interlayer dielectric (ILD) features. In general, low-κ dielectrics exhibit a dielectric constant that is less than that of SiO₂.

FIG. 1 provides an example of a section of a chemical mechanical polishing (or a planarization) tool. A wafer carrier 105 includes a wafer retaining ring 110 for a semiconductor wafer. The wafer carrier 105 rotates a wafer surface against a CMP pad 115 on a surface of a rotating platen 120. A slurry dispenser 125 can apply a mixture and/or slurry of material to the surface of the CMP pad 115. The mechanical polishing tool can also apply a downward mechanical pressure that pushes the face of the wafer carrier 105 comprising the wafer retaining ring 110 and a semiconductor wafer toward the CMP pad 115. The semiconductor wafer is within the retaining ring and not visible in this view.

Over time, the wafer retaining ring 110 can become grooved and/or worn down. The inability to predict retaining ring failure can lead to the loss of semiconductor wafers undergoing processing when a retaining ring fails. Alternatively, early replacement of retaining rings 110, can lead to unnecessary expense when retaining rings 110 that are still within their useful lifetime are replaced. Over the course of numerous manufacturing processes, losses can become significant. Surface ware of wafer retaining rings can cause significant process variability throughout the lifetime of the retaining ring due, for example, to slurry transport variability and wafer location variance in reference to the retaining ring surface.

A wafer retaining ring 110 can have different active surface profiles (such as teeth, toothless, gear, or fanned angles (at varying degrees and depths) shapes) and be comprised of materials having differing physical characteristics (e.g., hardness, elasticity, wear rate). The active surface of a wafer retaining ring 110 is the surface that contacts the CMP pad 115. The different shapes of the active surface profiles change how the wafer retaining ring 110 interacts with a selected etching/polishing solution/slurry. Some active surface features can create suction that draws the etching/polishing solution/slurry toward the face of the wafer being processed. Materials for the retaining ring 110 include polymeric materials, such as, for example polyethylene terephthalate (PET), polyphenylene (PPS), and polyether ether ketone (PEEK) which can exhibit different mechanical properties. The different shapes and material characteristics, for wafer retaining rings 110 can exhibit different wear characteristics under different processing conditions (i.e., process recipes: temperatures, pressure, etchant composition, slurry composition, spin rates, processing times, wafer compositions, and other variables).

FIG. 2A provides a wafer retaining ring wear characterization system. The wafer retaining ring wear characterization system includes rotatable bearings 205 on which a retaining ring can be placed and rotated by a motor (not shown) attached to a rotating head 210 that can cause the retaining ring to rotate. An idler (not shown) can be attached to a second rotatable head 215. A third rotatable head 220 can be one that freely rotates. A wafer retaining ring wear characterization system can include other numbers of rotating heads 220, such as zero, two, three, etc. Although three are shown (and one is obscured by the angle of observation), a wafer retaining ring wear characterization system can also comprise other number of rotatable bearings 205, such as three, five, six, etc. Rotatable bearings 205 can be mounted in a housing 225. Although a circular housing 225 is shown, other shapes are possible. A profilometer 230 is mounted on a pedestal 235. An imaging device, such as a profilometer 230, can comprise a laser. The profilometer 230 can be operably coupled (either wired or wirelessly) to a compute device (or system) 240 that is able to record image data and image location data from the profilometer 230. The compute device 240 is capable of causing the rotation mechanism, such as the motor, to rotate the wafer retaining ring 245. The compute device (or system) 240 can be one that includes display, user input devices, and software that allows two dimensional (2D) and/or three dimensional (3D) images of a retaining ring to be displayed. The compute system can be capable of displaying data that comprises coordinates of points on surfaces of the wafer retaining ring. The coordinates in the data output can be in reference to the wafer retaining ring's location in relation to the profilometer 230, so that their cardinality between measurement specifics is determined by the systems configuration and external variables.

FIG. 2B illustrates a top-down view of the wafer retaining ring wear characterization system of FIG. 2A in which a wafer retaining ring 245 has been mounted. The wafer retaining ring 245 is on the rotatable bearings 205 (not visible in this view) and is capable of rotation within the housing 225. The motor (not shown) attached to a rotating head 210 that can cause the wafer retaining ring 245 to rotate. The idler (not shown) can be attached to a second rotatable head 215 can slow /d/ or stop the rotation of the wafer retaining ring 245.

Other designs are possible for the wafer retaining ring wear characterization system, such as one in which a motor is attached to the pedestal 235 and is capable of causing the profilometer 230 (laser/camera or other device) to rotate.

FIGS. 3A and 3B show 2D and 3D wear representations for example wafer retaining rings that have been employed in a CMP process, removed, and analyzed using a wafer retaining ring wear characterization system according to FIGS. 2A-2B. The exemplary wafer retaining ring has a tooth shape at its edge which has developed an unwanted trench during the CMP process. FIG. 2A illustrates a 2D wear pattern for the same wafter retaining ring as FIG. 2B, which shows a 3D illustration of the wafer retaining ring. In FIG. 2A, a graph 300 of distance inward along a radius of the ring (distance 1) versus distance at a 90 degree angle (distance 2) (305) (the plot shown as a dashed line) shows the problematic wear feature 315. In this example, the wear feature 315 is a groove. The data obtained from a wafer retaining ring wear characterization system can include, for example, the width of the wear feature 321, the depth of the wear feature 320 (determined, for example, from the average height of the surrounding wafer retaining ring surface), and the distance from the edge of the wafer retaining ring of the wear feature 325. FIG. 2B shows a 3D image 350 of the wafer retaining ring 330. The wear feature 315 can be seen at the edges of the teeth of the retaining ring 330. A remaining tooth length 322 can be determined. From the 3D image, for example.

FIG. 4 diagrams a method for analyzing the wear on wafer retaining rings used in CMP processes. A wafer retaining ring is selected for analysis 400. The wafer retaining ring is run on a selected CMP process 405. The wafer retaining ring is removed from the CMP tool and placed in a wafer retaining ring wear characterization system, for example, a system shown in and described herein with respect to FIGS. 2A-2B. The wafer retaining ring is analyzed in a wafer retaining ring wear characterization system 410. Data is obtained, such as the data showing morphology of the surface of the wafer retaining ring, for example, as shown in FIGS. 3A and 3B. A new wafer retaining ring is selected for analysis that has different physical characteristics than the prior wafer retaining ring(s) that have been analyzed, the selected CMP process is rerun using the new wafer retaining ring, and the new wafer retaining ring is analyzed 415. As before, the new wafer retaining ring can be analyzed using a system shown in and described herein with respect to FIGS. 2A-2B, and data can be obtained showing morphology of the surface of the wafer retaining ring, for example, as shown in FIGS. 3A and 3B. This process can be repeated a number of times on different types of wafer retaining rings to select a wafer retaining ring for a CMP process 420. The performance of a specific wafer retaining ring in a CMP process can also be considered in the selection of a wafer retaining ring for a specific CMP process. Additionally, data over time in the selected CMP process for a selected wafer retaining ring can be analyzed to determine a wafer retaining ring lifetime in a selected CMP process. Selection of appropriate shape and material composition for a process recipe can lengthen the time between retaining ring changes. Additionally, the wafer retaining ring in employed in the CMP process for different amounts of time and the wafer retaining ring is pulled from the process and analyzed, for example, the using a system shown in and described herein with respect to FIGS. 2A-2B, and data can be obtained showing morphology of the surface of the wafer retaining ring, for example, as shown in FIGS. 3A and 3B. A wafer retaining ring can be replaced, for example, according to a schedule determined by balancing costs for maximal lifetime with wafer retaining ring failure cost. A method can include determining a number of times chemical a selected wafer retaining ring is to be used in a mechanical polish process.

FIG. 5 depicts an example compute system. The compute system can be a system used for running equipment in a semiconductor fabrication plant. Additionally, instructions for operating a wafer retaining ring characterization system, or for performing one or more aspects of the process described in FIG. 4 can be stored and/or run on the compute system. A compute system 500 can include more, different, or fewer features than the ones described with respect to FIG. 5.

Compute system 500 includes processor 510, which provides processing, operation management, and execution of instructions for system 500. Processor 510 can include any type of microprocessor, CPU (central processing unit), GPU (graphics processing unit), processing core, or other processing hardware to provide processing for system 500, or a combination of processors or processing cores. Processor 510 controls the overall operation of system 500, and can be or include, one or more programmable general-purpose or special-purpose microprocessors, DSPs, programmable controllers, ASICs, programmable logic devices (PLDs), or the like, or a combination of such devices.

In one example, system 500 includes interface 512 coupled to processor 510, which can represent a higher speed interface or a high throughput interface for system components needing higher bandwidth connections, such as memory subsystem 520 or graphics interface components 540, and/or accelerators 542. Interface 512 represents an interface circuit, which can be a standalone component or integrated onto a processor die. Where present, graphics interface 540 interfaces to graphics components for providing a visual display to a user of system 500. In one example, the display can include a touchscreen display.

Accelerators 542 can be a fixed function or programmable offload engine that can be accessed or used by a processor 510. For example, an accelerator among accelerators 542 can provide data compression (DC) capability, cryptography services such as public key encryption (PKE), cipher, hash/authentication capabilities, decryption, or other capabilities or services. In some cases, accelerators 542 can be integrated into a CPU socket (e.g., a connector to a motherboard (or circuit board, printed circuit board, mainboard, system board, or logic board) that includes a CPU and provides an electrical interface with the CPU). For example, accelerators 542 can include a single or multi-core processor, graphics processing unit, logical execution unit single or multi-level cache, functional units usable to independently execute programs or threads, application specific integrated circuits (ASICs), neural network processors (NNPs), programmable control logic, and programmable processing elements such as field programmable gate arrays (FPGAs) or programmable logic devices (PLDs). Accelerators 542 can provide multiple neural networks, CPUs, processor cores, general purpose graphics processing units, or graphics processing units can be made available for use by artificial intelligence (AI) or machine learning (ML) models.

Memory subsystem 520 represents the main memory of system 500 and provides storage for code to be executed by processor 510, or data values to be used in executing a routine. Memory subsystem 520 can include one or more memory devices 530 such as read-only memory (ROM), flash memory, one or more varieties of random access memory (RAM) such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM) and/or or other memory devices, or a combination of such devices. Memory 530 stores and hosts, among other things, operating system (OS) 532 that provides a software platform for execution of instructions in system 500, and stores and hosts applications 534 and processes 536. In one example, memory subsystem 520 includes memory controller 522, which is a memory controller to generate and issue commands to memory 530. The memory controller 522 can be a physical part of processor 510 or a physical part of interface 512. For example, memory controller 522 can be an integrated memory controller, integrated onto a circuit within processor 510.

System 500 can also optionally include one or more buses or bus systems between devices, such memory buses, graphics buses, and/or interface buses. Buses or other signal lines can communicatively or electrically couple components together, or both communicatively and electrically couple the components. Buses can include physical communication lines, point-to-point connections, bridges, adapters, controllers, or other circuitry or a combination. Buses can include, for example, one or more of a system bus, a peripheral component interface (PCI) or PCI express (PCIe) bus, a Hyper Transport or industry standard architecture (ISA) bus, a small computer system interface (SCSI) bus, a universal serial bus (USB), or a Firewire bus.

In one example, system 500 includes interface 514, which can be coupled to interface 512. In one example, interface 514 represents an interface circuit, which can include standalone components and integrated circuitry. In one example, user interface components or peripheral components, or both, couple to interface 514. Network interface 550 provides system 500 the ability to communicate with remote devices (e.g., servers or other compute devices) over one or more networks. Network interface 550 can include an Ethernet adapter, wireless interconnection components, cellular network interconnection components, USB, or other wired or wireless standards-based or proprietary interfaces. Network interface 550 can transmit data to a device that is in the same data center or rack or a remote device, which can include sending data stored in memory.

Some examples of network interface 550 are part of an infrastructure processing unit (IPU) or data processing unit (DPU), or used by an IPU or DPU. An xPU can refer at least to an IPU, DPU, GPU, GPGPU (general purpose compute devices on graphics processing units), or other processing units (e.g., accelerator devices). An IPU or DPU can include a network interface with one or more programmable pipelines or fixed function processors to perform offload of operations that can have been performed by a CPU. The IPU or DPU can include one or more memory devices.

In one example, system 500 includes one or more input/output (I/O) interface(s) 560. I/O interface 560 can include one or more interface components through which a user interacts with system 500 (e.g., audio, alphanumeric, tactile/touch, or other interfacing). Peripheral interface 570 can include additional types of hardware interfaces, such as, for example, interfaces to semiconductor fabrication equipment and/or electrostatic charge management devices.

In one example, system 500 includes storage subsystem 580. Storage subsystem 580 includes storage device(s) 584, which can be or include any conventional medium for storing data in a nonvolatile manner, such as one or more magnetic, solid state, and/or optical based disks. Storage 584 can be generically considered to be a “memory,” although memory 530 is typically the executing or operating memory to provide instructions to processor 510. Whereas storage 584 is nonvolatile, memory 530 can include volatile memory (e.g., the value or state of the data is indeterminate if power is interrupted to system 500). In one example, storage subsystem 580 includes controller 582 to interface with storage 584. In one example controller 582 is a physical part of interface 512 or processor 510 or can include circuits or logic in both processor 510 and interface 514.

A power source (not depicted) provides power to the components of system 500. More specifically, power source typically interfaces to one or multiple power supplies in system 500 to provide power to the components of system 500.

Examples of systems may be implemented in various types of compute devices, smart phones, tablets, personal computers, and networking equipment, such as switches, routers, racks, and blade servers such as those employed in a data center and/or server farm environment.

EXAMPLES

A system can comprise: a housing; a rotation mechanism within the housing wherein the rotation mechanism is capable of rotating a wafer retaining ring that is used in a semiconductor fabrication chemical mechanical polish process; an imaging device that is capable of imaging surfaces of a wafer retaining ring that is used in a semiconductor fabrication chemical mechanical polish processes; and a compute device operably connected to the rotation mechanism and operably connected to the imaging device, wherein the compute device is capable of storing data from the imaging device, and wherein the compute device is capable of causing the rotation mechanism to rotate the wafer retaining ring. The rotation mechanism can comprise rotatable bearings. The rotation mechanism can comprise a motor. The imaging device can comprise a laser. The imaging device can be a profilometer. The compute device can be capable of displaying data that comprises coordinates of points on surfaces of the wafer retaining ring.

A method can comprise: selecting a wafer retaining ring for analysis; employing the wafer retaining ring in a chemical mechanical polish process; collecting data comprising surface characteristics of the wafer retaining ring; and repeating the process of selecting a wafer retaining ring, employing the wafer retaining ring in a chemical mechanical polish process, and collecting data comprising surface characteristics of the wafer retaining ring. Collecting data comprising surface characteristics of the wafer retaining ring can include scanning surfaces of the wafer retaining ring with a profilometer. The method can also include selecting a wafer retaining ring for a chemical mechanical polish process based on data comprising surface characteristics of the wafer retaining ring. The method can also include determining a number of times a selected wafer retaining ring is to be used in a chemical mechanical polish process. The wafer retaining ring can be comprised of a polymeric material.

At least one machine-readable storage medium can comprise non-transitory instructions, that when executed by a processor, cause a device to: rotate a wafer retaining ring in a wafer retaining ring analysis device capable of imaging surfaces of a wafer retaining ring wherein the wafer retaining ring can be used in a semiconductor fabrication chemical mechanical polish process; store surface image data from the imaging device; and output surface image data from the imaging device. The wafer retaining ring analysis device can comprise a profilometer that is capable of imaging surfaces of a wafer. The wafer retaining ring analysis device can comprise rotatable bearings that are capable of causing the wafer retaining ring to rotate in the wafer retaining ring analysis device. The wafer retaining ring analysis device can comprise a motor that is capable of causing the rotation of a wafer retaining ring. The at least one machine-readable storage medium can also include instructions that cause data from the imaging device to be output as a graph.

Besides what is described herein, various modifications can be made to what is disclosed and implementations without departing from their scope. Therefore, the illustrations and examples herein should be construed in an illustrative, and not a restrictive sense.