MEMS acoustic sensor with integrated back cavity

Monolithically integrated multi-sensor device on a semiconductor substrate and method therefor

Cell phone having a monolithically integrated multi-sensor device on a semiconductor substrate and method therefor

Transportation device having a monolithically integrated multi-sensor device on a semiconductor substrate and method therefor

Complementary metal oxide semiconductor (CMOS) ultrasonic transducers and methods for forming the same

MEMS devices and methods for forming same

MEMS integrated pressure sensor and microphone devices and methods of forming same

Memory cells, methods of fabrication, semiconductor device structures, and memory systems

Parallel shunt paths in thermally assisted magnetic memory cells

Reader sensor structure and its method of construction

Cell design for embedded thermally-assisted MRAM

Vertical hall effect element with structures to improve sensitivity

Logic chip including embedded magnetic tunnel junctions

Magnetic memory element

Cell design for embedded thermally-assisted MRAM

Magnetic junctions having insertion layers and magnetic memories using the magnetic junctions

Methods of manufacturing magnetoresistive random access memory devices

Magnetoresistive element and magnetic memory

Storage element and memory

Memory cell having nonmagnetic filament contact and methods of operating and fabricating the same

Forming magnetic microelectromechanical inductive components

Chip package with isolated pin, isolated pad or isolated chip carrier and method of making the same

Packaging for an electronic device

Logic chip including embedded magnetic tunnel junctions

Non-volatile memory devices and methods of fabricating the same

Interconnect structure for stacked device and method

Imaging sensor structure and method

Image sensor with stacked grid structure

Solid-state imaging devices

Image sensor with trenched filler grid within a dielectric grid including a reflective portion, a buffer and a high-K dielectric

Optical sensors for detecting relative motion and/or position and methods and systems for using such optical sensors

Solid state imaging device and method for manufacturing solid state imaging device

Low profile image sensor

Low profile sensor module and method of making same

Solid state imaging device and manufacturing method, and electronic apparatus

Dielectric film for image sensor

Image pickup module and image pickup unit

Image sensor device and method

Semiconductor package including an image sensor and a holder with stoppers

Monolithic sun sensors assemblies thereof

Image sensor device and method

Optical sensor

Solid-state image sensing device and semiconductor display device

Low cross-talk for small pixel barrier detectors

Imaging device

Solid state imaging device, method of manufacturing the same, and imaging apparatus

Integrated image sensor

Optical absorbers

Interconnect structure for connecting dies and methods of forming the same

Seal ring structure with rounded corners for semiconductor devices

Light sensor with vertical diode junctions

Infrared detector made up of suspended bolometric micro-plates

Gate contact for a semiconductor device and methods of fabrication thereof

Power semiconductor devices incorporating single crystalline aluminum nitride substrate

Methods and apparatus for congestion-aware buffering using voltage isolation pathways for integrated circuit designs with multi-power domains

Semiconductor wafer, semiconductor process and semiconductor package

Method of fabricating a FinFET device

Nonvolatile semiconductor memory device and method of manufacturing the same

Varied STI liners for isolation structures in image sensing devices

Method and structure for nitrogen-doped shallow-trench isolation dielectric

Semiconductor device

Devices including a diamond layer

Deep trench isolation

Silicon recess ETCH and epitaxial deposit for shallow trench isolation (STI)

Semiconductor devices and methods of manufacturing the same

Semiconductor device and method of fabricating the same

Microelectronic elements with master/slave configurability

Magnetic core inductor (MCI) structures for integrated voltage regulators

Inductor with magnetic material

Inductor system and method

Semiconductor device and method of forming an inductor on polymer matrix composite substrate

Component-embedded substrate

Folded conical inductor

Methods of forming under device interconnect structures

Semiconductor device

Capacitor using barrier layer metallurgy

Integrated capacitor

Structure of metal gate MIM

Stacked semiconductor device and method of forming the same

Transmission line formed adjacent seal ring

Self aligned capacitor fabrication

Deposition of anisotropic dielectric layers orientationally matched to the physically separated substrate

Manufacturing method of semiconductor device and semiconductor device

Semiconductor device

Resistor and metal-insulator-metal capacitor structure and method

Metal-insulator-metal (MIM) capacitor

Dual three-dimensional (3D) resistor and methods of forming

Structure of resistor

Methods of forming doped elements of semiconductor device structures

Strained silicon nFET and silicon germanium pFET on same wafer

Electrical leakage reduction in stacked integrated circuits having through-silicon-via (TSV) structures

Metal structures and methods of using same for transporting or gettering materials disposed within semiconductor substrates

Methods of forming a protection layer to protect a metal hard mask layer during lithography reworking processes

Stacked wafer with coolant channels

Layout optimization of a main pattern and a cut pattern

Methods of laser marking semiconductor substrates

Wafer stack protection seal

Engineered substrates for semiconductor epitaxy and methods of fabricating the same

Layer arrangement

Semiconductor wafer and method of producing same

Methods for forming a stress-relieved film stack by applying cutting patterns

Wafer and integrated circuit chip having a crack stop structure

Die preparation for wafer-level chip scale package (WLCSP)

Packaging mechanisms for dies with different sizes of connectors

Method of forming through substrate vias (TSVs) and singulating and releasing die having the TSVs from a mechanical support substrate

Chip package structure and manufacturing method thereof

Shielding for through-silicon-via

System and method for optimization of an imaged pattern of a semiconductor device

Wafer and film coating method of using the same

Method and system for transient voltage suppression

Semiconductor wafer with a layer of AlGaN and process for producing it

Nanocrystalline diamond three-dimensional films in patterned semiconductor substrates

Precursor composition for deposition of silicon dioxide film and method for fabricating semiconductor device using the same

Metal deposition on substrates

Adhesion layer to minimize dielectric constant increase with good adhesion strength in a PECVD process

Passivation layer for harsh environments and methods of fabrication thereof

Formation of a high aspect ratio contact hole

Chip package and method for forming the same

Semiconductor device including RDL along sloped side surface of semiconductor die for Z-direction interconnect

Differential excitation of ports to control chip-mode mediated crosstalk

High-frequency module

Semiconductor packages and methods of packaging semiconductor devices

Chip package and method for manufacturing the same

Direct external interconnect for embedded interconnect bridge package

Semiconductor packages and methods of packaging semiconductor devices

Lead frame for semiconductor package with enhanced stress relief

Low CTE interposer without TSV structure

No-exposed-pad quad flat no-lead (QFN) packaging structure and method for manufacturing the same

Insulated bump bonding

Method of manufacturing semiconductor device

Packaged device comprising non-integer lead pitches and method of manufacturing the same

Power overlay structure and method of making same

Power overlay structure and method of making same

Semiconductor device

Semiconductor device with thick bottom metal and preparation method thereof

Package device including an opening in a flexible substrate and methods of forming the same

Stack die package

Semiconductor package and fabrication method thereof

Semiconductor devices and methods of making the same

Packages with molding material forming steps

Package on-package with cavity in interposer

Semiconductor package assembly with decoupling capacitor

Semiconductor device package and method

Method for manufacturing a semiconductor chip with each contact pad having a pad cell associated therewith

Semiconductor device package and method

Semiconductor package structure

Semiconductor device and method of using partial wafer singulation for improved wafer level embedded system in package

Polymer thermal interface material having enhanced thermal conductivity

Semiconductor device and manufacturing method thereof

Paste thermal interface materials

Molded heat spreaders

Thermosetting resin compositions with low coefficient of thermal expansion

Systems and methods for fabricating semiconductor devices having larger die dimensions

Methods and apparatus of packaging semiconductor devices

Ultra-low resistivity contacts

Semiconductor device including insulating films with different moisture resistances and fabrication method thereof

Methods of forming wafer level underfill materials and structures formed thereby

Method and apparatus for a conductive pillar structure

Electronic assembly with copper pillar attach substrate

Bumpless build-up layer (BBUL) semiconductor package with ultra-thin dielectric layer

Chip arrangements

Low cost and ultra-thin chip on wafer on substrate (CoWoS) formation

Semiconductor packages and methods of packaging semiconductor devices

System-in-package with interposer pitch adapter

Semiconductor device with post-passivation interconnect structure and method of forming the same

Method and apparatus for a conductive bump structure

Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices

Package on-package structure

Surface treatment in electroless process for adhesion enhancement

Package-on-package structure and method of forming same

Integrated circuit structure having dies with connectors

Semiconductor device having a die and through substrate-via

Wafer-level package device having high-standoff peripheral solder bumps

Packaging devices, methods of manufacture thereof, and packaging methods

Package-on-package structure

Semiconductor device and method of forming a dual UBM structure for lead free bump connections

Semiconductor device and method of forming UBM structure on back surface of TSV semiconductor wafer

Through via structure including a conductive portion and aligned solder portion

Adhesion between post-passivation interconnect structure and polymer

Multi-chip module with self-populating positive features

Package on-package structures and methods for forming the same

Package-on-package with via on pad connections

Package on-package joint structure with molding open bumps

Packaging devices and methods of manufacture thereof

Rectifier diode

Sputter etch processing for heavy metal patterning in integrated circuits

Interconnect structure and method

Conductive line system and process

Integrated circuit structure and formation

Chemical direct pattern plating interconnect metallization and metal structure produced by the same

Method of forming hybrid diffusion barrier layer and semiconductor device thereof

Wafer-level die attach metallization

Method of back-end-of-line (BEOL) fabrication, and devices formed by the method

Method to increase interconnect reliability

Method of forming interconnection structure having notches for semiconductor device

Electro-migration barrier for Cu interconnect

Semiconductor device and manufacturing method having copper interconnects with metal film, barrier metal, and metal caps

Multi-layer barrier layer stacks for interconnect structures

Copper interconnect structures and methods of making same

Interconnect structure and method of forming the same

Methods and structures to facilitate through-silicon vias

Forming fence conductors using spacer etched trenches

Interconnect structure and method of forming same

WLCSP interconnect apparatus and method

Method for wafer separation

Oriented crystal nanowire interconnects

Semiconductor package structure and method of manufacturing the same

Semiconductor device channels

Pillar structure for use in packaging integrated circuit products and methods of making such a pillar structure

Forming fence conductors in an integrated circuit

Semiconductor device with dummy lines

Pitch-halving integrated circuit process and integrated circuit structure made thereby

System and method for arbitrary metal spacing for self-aligned double patterning

Semiconductor devices and methods of manufacture thereof

Structure and method for a low-K dielectric with pillar-type air-gaps

Damascene conductor for a 3D device

3-D IC device with enhanced contact area

Pattern modification with a preferred position function

Anisotropic conductor and method of fabrication thereof

Semiconductor device and layout design system

Patterning approach for improved via landing profile

Interconnect structure and method of forming the same

Semiconductor device and method of forming WLCSP with semiconductor die embedded within interconnect structure

Systems and methods for high-speed, low-profile memory packages and pinout designs

Stubby pads for channel cross-talk reduction

Dual damascene gap filling process

Microelectromechanical system devices having through substrate vias and methods for the fabrication thereof

Interconnect structures with polymer core

Through silicon vias

Semiconductor device

Chip package-in-package and method thereof

Integrated structure with a silicon-through via

Integrated circuit layout

Chip arrangement, wafer arrangement and method of manufacturing the same

Metal cap apparatus and method

Through-silicon via with sidewall air gap

Semiconductor structure

Interconnect structure with kinked profile

Interlayer conductor and method for forming

Method and apparatus for back end of line semiconductor device processing

Single mask package apparatus and method

Semiconductor package and fabrication method thereof

Interconnect structure for stacked device

Fan-out interconnect structure and method for forming same

Stress tuning for reducing wafer warpage

Patterning approach to reduce via to via minimum spacing

Wafer level chip scale packaging intermediate structure apparatus and method

Interlayer conductor structure and method

Semiconductor device manufacturing method and semiconductor mounting substrate

Through-silicon vias and interposers formed by metal-catalyzed wet etching

Semiconductor device

Semiconductor package and package on package having the same

Three-dimensional semiconductor architecture

Semiconductor device channels

Multiple-patterned semiconductor device channels

Semiconductor package with top-side insulation layer

Stacked microelectronic packages having sidewall conductors and methods for the fabrication thereof

Package-on-package structure with reduced height

Interconnect apparatus and method

Air trench in packages incorporating hybrid bonding

Gold die bond sheet preform

Chip arrangement and a method of manufacturing a chip arrangement

Laser die backside film removal for integrated circuit (IC) packaging

Wiring structures including spacers and an airgap defined thereby, and methods of manufacturing the same