NEXPERIA B.V.

A SUBSTRATE, IN PARTICULAR A LEAD-FRAME SUBSTRATE USED IN A SEMICONDUCTOR PACKAGE FOR MOUNTING A SEMICONDUCTOR DIE ELEMENT

METHOD OF MANUFACTURING A SEMICONDUCTOR PACKAGE AND SUCH SEMICONDUCTOR PACKAGE

CONTINUOUS TIME COMPARATOR WITH IMPROVED PROPAGATION DELAY FOR A GIVEN CURRENT

LATERAL ORIENTED TRANSISTOR EMBODIED IN A SEMICONDUCTOR MATERIAL AND A CORRESPONDING SEMICONDUCTOR PACKAGE

SEMICONDUCTOR PACKAGE AND A BOND CLIP FOR USE IN THE SEMICONDUCTOR PACKAGE

MODULE FOR AN ELECTRIC CIRCUIT

SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE

SEMICONDUCTOR DEVICE AND PACKAGE WITH KELVIN SOURCE CONNECTION

PACKAGE STRUCTURE FOR A SEMICONDUCTOR DEVICE

ENCAPSULATED SEMICONDUCTOR PACKAGE

METHOD OF MANUFACTURING A SEMICONDUCTOR PACKAGE HAVING A CONNECTION PIN AND CORRESPONDING SEMICONDUCTOR PACKAGE

LATERAL ORIENTED METAL-OXIDE-SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING LATERAL ORIENTED METAL-OXIDE-SEMICONDUCTOR

SEMICONDUCTOR PACKAGE, A HALF BRIDGE CLIP, AND A METHOD FOR MANUFACTURING SAID SEMICONDUCTOR PACKAGE

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND CORRESPONDING SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR PACKAGE

WIRE-BOND STRUCTURE FOR POWER PACKAGES TO REDUCE RDSON

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

METHOD OF LIMITING STARTUP INRUSH CURRENT AND A SYSTEM FOR LIMITING STARTUP INRUSH CURRENT

SWITCHED MODE POWER SUPPLY CIRCUIT HAVING AN ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT AND METHOD

METHOD AND AN ELECTRONIC SYSTEM FOR SOFT RECOVERY FOR SWITCHED MODE POWER SUPPLIES

SWITCHED MODE POWER SUPPLY ARRANGED FOR EFFICIENTLY POWERING A RANGE OF LOADS AND METHOD OF OPERATING SUCH

Semiconductor Package

PICK-AND-PLACE APPARATUS WITH FORCE MEASUREMENT

SYSTEM FOR DETERMINING AN ORIENTATION OF A DEVICE

PICKUP UNIT

METHOD OF MANUFACTURING A SINGULATED SEMICONDUCTOR PRODUCT AS WELL AS A SINGULATED SEMICONDUCTOR PRODUCT OBTAINED BY THIS METHOD

CLIP-BONDED SEMICONDUCTOR PACKAGE AND CORRESPONDING METHOD OF MANUFACTURING SUCH A SEMICONDUCTOR PACKAGE

SEMICONDUCTOR DEVICE AS WELL AS A METHOD OF MANUFACTURING SUCH SEMICONDUCTOR DEVICE

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SUCH SEMICONDUCTOR DEVICE

Semiconductor Package

METHOD OF MANUFACTURING A SPLIT GATE TRENCH SEMICONDUCTOR COMPRISING A THICKER INTER-POLY OXIDE, IPO LAYER AND A SEMICONDUCTOR DEVICE COMPRISING A THICKER IPO LAYER

PRESS FIT PIN AND METHOD OF ASSEMBLING A PRESS FIT PIN

INTERACTIVE DISPLAY OF ELECTRICAL PROPERTIES OF AN ELECTRICAL COMPONENT

METHOD OF FABRICATING A SEMICONDUCTOR INTEGRATED CIRCUITS PACKAGE

METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR, MOSFET, HAVING A REDUCED ON-RESISTANCE AS WELL AS A REDUCED OUTPUT CAPACITANCE, AS WELL AS A CORRESPONDING METHOD AND A SEMICONDUCTOR PACKAGE

SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING OF THE SEMICONDUCTOR DEVICE

SEMICONDUCTOR DEVICE WITH PLATED CLIP AND FLIP-CHIP INTERCONNECT ON LEADFRAME

SEMICONDUCTOR DEVICE AND METHOD OF ION IMPLEMENTATION IN A SEMICONDUCTOR DEVICE

A METHOD OF MANUFACTURING BOTTOM THICK OXIDE, BTO, IN A TRENCH OF A SEMICONDUCTOR MATERIAL AS WELL AS FIELD OXIDE, FOX, ON TOP OF THE SEMICONDUCTOR MATERIAL, AS WELL AS A RELATED SEMICONDUCTOR DEVICE

HIGH ELECTRON MOBILITY TRANSISTOR, HEMT, STRUCTURE HAVING A GATE, A SOURCE AND A DRAIN, AS WELL AS A METHOD OF OPERATING SUCH A HEMT STRUCTURE

LEADLESS PACKAGE COMPRISING A FIRST AND A SECOND SEMICONDUCTOR DIE, WHEREIN A GALVANIC ISOLATION IS PROVIDED BETWEEN THOSE SEMICONDUCTOR DIES, AS WELL AS A CORRESPONDING METHOD

A LEADLESS PACKAGE COMPRISING A FIRST AND A SECOND SEMICONDUCTOR DIE, WHEREIN A GALVANIC COUPLING IS PROVIDED BETWEEN THOSE SEMICONDUCTOR DIES, AS WELL AS A CORRESPONDING METHOD

PACKAGE COMPRISING A FIRST AND A SECOND SEMICONDUCTOR DIE, WHEREIN A GALVANIC COUPLING IS PROVIDED BETWEEN THOSE SEMICONDUCTOR DIES, AS WELL AS A CORRESPONDING METHOD

LEADLESS PACKAGE COMPRISING A FIRST AND A SECOND SEMICONDUCTOR DIE, WHEREIN A GALVANIC COUPLING IS PROVIDED BETWEEN THOSE SEMICONDUCTOR DIES, AS WELL AS A CORRESPONDING METHOD

FLAT CONTACT TRENCH MOSFET AND MANUFACTURING METHOD THEREOF

EDGE TERMINATION STRUCTURE

CROSS-COUPLED LATCH CHARGE PUMP AS WELL AS A METHOD OF OPERATING SUCH A CROSS-COUPLED LATCH CHARGE PUMP

ADAPTIVE MPPT TIMER OF A POWER MANAGER FOR AN ENERGY HARVESTING SYSTEM AND A METHOD OF USING SUCH ADAPTIVE MPPT TIMER

Semiconductor Package and a Method of Manufacturing the Semiconductor Package

SEMICONDUCTOR DEVICE WITH CONTROLLED BOND LINE THICKNESS USING SPACERS AND RECESSES

SEMICONDUCTOR DEVICE AND A METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR IMPLEMENTING SUCH SEMICONDUCTOR DEVICE

VALLEY CURRENT LIMIT DETECTION SCHEME FOR SWITCHING REGULATORS

SEMICONDUCTOR DEVICE AND METHOD OF FORMING SELF-ALIGNED CONTACT IN SEMICONDUCTOR DEVICE

SUPER JUNCTION REGION FOR LOW CAPACITANCE ESD SEMICONDUCTOR DEVICES

AUTONOMOUS BATTERY LIFESPAN BOOSTER

THREE PIN CURRENT TRIGGERED TVS PROTECTION SEMICONDUCTOR DEVICE

PFM Transition Hysteresis Scheme for Peak-Current Mode Buck Converters

SEMICONDUCTOR DEVICE AND METHOD OF PROVIDING A PLUG IN A SEMICONDUCTOR DEVICE

SWITCHING STAGE OF A SWITCHED MODE POWER SUPPLY, SMPS, AS WELL AS AN SMPS AND CORRESPONDING METHOD

ESD PROTECTION SEMICONDUCTOR DEVICE AND ESD PROTECTION CIRCUIT

MODULE FOR AN ELECTRIC CIRCUIT HAVING A PLANARLY STACKED STRUCTURE FOR POWER PACKAGE TERMINALS, AS WELL AS A RELATED POWER MODULE AND METHOD OF MANUFACTURING SUCH A MODULE

DUAL COOLED MOSFET FOR LOW RDSON AND LOW THERMAL POWER

Chip

PASSGATE SWITCH GATE-DRIVER CONTROL FOR PREVENTING NO-OVERSHOOT WHEN SWITCHING

CLIP

TRENCH ELECTROSTATIC DISCHARGE PROTECTION DEVICE

SUPPRESSION OF AUTO-DOPING DURING EPITAXIAL GROWTH OF EPITAXY LAYER IN A SEMICONDUCTOR DEVICE

SEMICONDUCTOR POWER DEVICE WITH TERMINATION RINGS

POWER STAGE DEVICE CLIP

OPEN BASE TRANSISTOR

HEAT EXCHANGER

OPEN-DRAIN REPEATER WITH EDGE ACCELERATOR FOR I2C APPLICATION

Lead Frame

SEMI-CONDUCTOR DEVICE

MULTI-LEVEL DI/DI CONTROL OF A POWER SEMICONDUCTOR DEVICE

SEMICONDUCTOR PACKAGE

Semiconductor Device and Manufacturing Method Thereof

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

SEMICONDUCTOR DEVICE AND METHOD OF FORMING A SEMICONDUCTOR DEVICE

POWER SEMICONDUCTOR DEVICE AND ASSOCIATED METHODS

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

SEMICONDUCTOR SWITCHING DEVICE IMPLEMENTING AN EDGE TERMINATION STRUCTURE

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

ADAPTIVE SLEW RATE DETECTION FOR A SYNCHRONOUS RECTIFIER OF A SYNCHRONOUS FLYBACK CONVERTER

METHOD OF MANUFACTURING SEMICONDUCTOR ASSEMBLIES

SEMICONDUCTOR DEVICE HAVING AN IMPROVED TERMINATION AREA, AS WELL AS A CORRESPONDING METHOD AND POWER DEVICE

SUBSTRATE FOR POWER SEMICONDUCTOR PACKAGING AND A PACKAGE CONTAINING SUCH SUBSTRATE

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

SEMICONDUCTOR PACKAGE

RECESSED REGIONS OF A JUNCTION TERMINATION EXTENSION FOR SEMICONDUCTOR DEVICES

TOP SURFACE OF A JUNCTION TERMINATION EXTENSION FOR SEMICONDUCTOR DEVICES

INTEGRATED CIRCUIT PACKAGE AND METHOD OF MANUFACTURING THEREOF

METHOD OF AND INTERMEDIATE FOR MANUFACTURING A SEMICONDUCTOR DIE PACKAGE

CLIP

CLIP

SEMICONDUCTOR PACKAGE FOR A PCB

EDGE TERMINATION REGION OF SUPERJUNCTION DEVICE

EDGE TERMINATION REGION OF SUPERJUNCTION DEVICE