Assignee profile:

MEARS TECHNOLOGIES, INC.

City:

Waltham, Massachusetts

Country:

United States

Published Applications:

28

Last publication date:

2011-08-11

Patent Grants:

27

Last grant date:

2013-03-05

Top Inventors for applications by MEARS TECHNOLOGIES, INC.

These are the the leading inventors for applications assigned to MEARS TECHNOLOGIES, INC.:

Recent patent applications by MEARS TECHNOLOGIES, INC.

MEARS TECHNOLOGIES, INC. based in Waltham, US has been assigned the rights to these inventions. The list includes both Pending Applications and Patent Grants:

#1 | 2011-08-11 ✅ Patent 8,389,974 granted on 2013-03-05
US20110193063A1
Electricity

Multiple-wavelength opto-electronic device including a superlattice

#2 | 2010-10-28
US20100270535A1
Electricity

ELECTRONIC DEVICE INCLUDING AN ELECTRICALLY POLLED SUPERLATTICE AND RELATED METHODS

#3 | 2008-10-23 ✅ Patent 7,812,339 granted on 2010-10-12
US20080258134A1
Electricity

Method for making a semiconductor device including shallow trench isolation (STI) regions with maskless superlattice deposition following STI formation and related structures

#4 | 2008-08-21 ✅ Patent 7,863,066 granted on 2011-01-04
US20080197341A1
Electricity

Method for making a multiple-wavelength opto-electronic device including a superlattice

#5 | 2008-08-21 ✅ Patent 7,880,161 granted on 2011-02-01
US20080197340A1
Electricity

Multiple-wavelength opto-electronic device including a superlattice

#6 | 2008-07-31 ✅ Patent 7,781,827 granted on 2010-08-24
US20080179664A1
Electricity

Semiconductor device with a vertical MOSFET including a superlattice and related methods

#7 | 2008-07-31 ✅ Patent 7,928,425 granted on 2011-04-19
US20080179588A1
Electricity

Semiconductor device including a metal-to-semiconductor superlattice interface layer and related methods

#8 | 2007-10-11 ✅ Patent 7,625,767 granted on 2009-12-01
US20070238274A1
Performing operations; transporting

Methods of making spintronic devices with constrained spintronic dopant

#9 | 2007-08-23 ✅ Patent 7,700,447 granted on 2010-04-20
US20070197006A1
Electricity

Method for making a semiconductor device comprising a lattice matching layer

#10 | 2007-08-23 ✅ Patent 7,718,996 granted on 2010-05-18
US20070194298A1
Electricity

Semiconductor device comprising a lattice matching layer

#11 | 2007-07-12 ✅ Patent 7,517,702 granted on 2009-04-14
US20070161138A1
Performing operations; transporting

Method for making an electronic device including a poled superlattice having a net electrical dipole moment

#12 | 2007-01-18 ✅ Patent 7,535,041 granted on 2009-05-19
US20070012999A1
Electricity

Method for making a semiconductor device including regions of band-engineered semiconductor superlattice to reduce device-on resistance

#13 | 2007-01-18 ✅ Patent 7,598,515 granted on 2009-10-06
US20070012912A1
Electricity

Semiconductor device including a strained superlattice and overlying stress layer and related methods

#14 | 2007-01-18 ✅ Patent 7,531,829 granted on 2009-05-12
US20070012911A1
Electricity

Semiconductor device including regions of band-engineered semiconductor superlattice to reduce device-on resistance

#15 | 2007-01-18 ✅ Patent 7,531,828 granted on 2009-05-12
US20070012909A1
Electricity

Semiconductor device including a strained superlattice between at least one pair of spaced apart stress regions

#16 | 2007-01-11 ✅ Patent 7,612,366 granted on 2009-11-03
US20070007508A1
Electricity

Semiconductor device including a strained superlattice layer above a stress layer

#17 | 2006-12-28 ✅ Patent 7,491,587 granted on 2009-02-17
US20060292818A1
Electricity

Method for making a semiconductor device having a semiconductor-on-insulator (SOI) configuration and including a superlattice on a thin semiconductor layer

#18 | 2006-11-30 ✅ Patent 7,514,328 granted on 2009-04-07
US20060270169A1
Electricity

Method for making a semiconductor device including shallow trench isolation (STI) regions with a superlattice therebetween

#19 | 2006-11-02 ✅ Patent 7,659,539 granted on 2010-02-09
US20060243963A1
Electricity

Semiconductor device including a floating gate memory cell with a superlattice channel

#20 | 2006-10-12 ✅ Patent 7,586,165 granted on 2009-09-08
US20060226502A1
Performing operations; transporting

Microelectromechanical systems (MEMS) device including a superlattice

#21 | 2006-09-14 ✅ Patent 7,531,850 granted on 2009-05-12
US20060202189A1
Electricity

Semiconductor device including a memory cell with a negative differential resistance (NDR) device

#22 | 2006-01-26 ✅ Patent 7,446,002 granted on 2008-11-04
US20060019454A1
Performing operations; transporting

Method for making a semiconductor device comprising a superlattice dielectric interface layer

#23 | 2006-01-12 ✅ Patent 7,433,729 granted on 2008-10-07
US20060008128A1
Physics

Infrared biometric finger sensor including infrared antennas and associated methods

#24 | 2005-08-25 ✅ Patent 7,303,948 granted on 2007-12-04
US20050184286A1
Electricity

Semiconductor device including MOSFET having band-engineered superlattice

#25 | 2005-08-11 ✅ Patent 7,435,988 granted on 2008-10-14
US20050173697A1
Electricity

Semiconductor device including a MOSFET having a band-engineered superlattice with a semiconductor cap layer providing a channel

#26 | 2005-04-28 ✅ Patent 7,436,026 granted on 2008-10-14
US20050087737A1
Electricity

Semiconductor device comprising a superlattice channel vertically stepped above source and drain regions

#27 | 2005-02-10 ✅ Patent 7,432,524 granted on 2008-10-07
US20050029511A1
Electricity

Integrated circuit comprising an active optical device having an energy band engineered superlattice

#28 | 2005-02-10 ✅ Patent 7,446,334 granted on 2008-11-04
US20050029509A1
Electricity

Electronic device comprising active optical devices with an energy band engineered superlattice

AssigneeID:

215527 ⎘