BROOKLINE, Massachusetts
United States
102
2026-04-30
The entities that hold a legal rights for patent applications filed by inventor HYTHA MAREK:
MAREK HYTHA from BROOKLINE, US has applied for patents for these inventions. The list has both pending applications and granted patents:
METHOD FOR MAKING SEMICONDUCTOR DEVICE INCLUDING AN ENRICHED SILICON 28 EPITAXIAL LAYER
#2 | 2026-02-12SEMICONDUCTOR DEVICE INCLUDING A SUPERLATTICE AND ENRICHED SILICON 28 EPITAXIAL LAYER
#3 | 2025-12-04SURFACE ACOUSTIC WAVE (SAW) DEVICES INCLUDING A SUPERLATTICE AND RELATED METHODS
#4 | 2025-12-04METHODS FOR MAKING SURFACE ACOUSTIC WAVE (SAW) DEVICES INCLUDING A SUPERLATTICE
#5 | 2025-08-28METHOD FOR MAKING SEMICONDUCTOR DEVICE INCLUDING A SUPERLATTICE AND ENRICHED SILICON 28 EPITAXIAL LAYER
#6 | 2025-08-14METHOD FOR MAKING SEMICONDUCTOR DEVICE WITH SELECTIVE ETCHING OF SUPERLATTICE TO ACCUMULATE NON-SEMICONDUCTOR ATOMS
#7 | 2025-07-31SEMICONDUCTOR DEVICE INCLUDING SUPERLATTICE SOURCE/DRAIN
#8 | 2025-07-31METHOD FOR MAKING SEMICONDUCTOR DEVICE INCLUDING SUPERLATTICE SOURCE/DRAIN
#9 | 2025-07-24SEMICONDUCTOR DEVICES INCLUDING COMPOUND SEMICONDUCTOR MATERIALS WITH A SUPERLATTICE LAYER
#10 | 2025-07-24SEMICONDUCTOR DEVICES WITH GROUP III-N AND SILICON DEVICE REGIONS ABOVE A SUPERLATTICE LAYER AND RELATED METHODS
#11 | 2025-07-24PIEZOELECTRIC DEVICES INCLUDING COMPOUND SEMICONDUCTOR MATERIALS AND A SUPERLATTICE LAYER
#12 | 2025-07-24METHOD FOR MAKING SEMICONDUCTOR DEVICES INCLUDING COMPOUND SEMICONDUCTOR MATERIALS WITH A SUPERLATTICE LAYER
#13 | 2025-07-24METHOD FOR MAKING SEMICONDUCTOR DEVICES WITH GROUP III-N AND SILICON DEVICE REGIONS ABOVE A SUPERLATTICE LAYER
#14 | 2025-07-24METHOD FOR MAKING SEMICONDUCTOR DEVICES INCLUDING COMPOUND SEMICONDUCTOR MATERIALS USING A SUPERLATTICE SEPARATION LAYER
#15 | 2025-04-17METHOD OF FABRICATING SEMICONDUCTOR DEVICES WITH ISOLATED SUPERLATTICE STRUCTURES
#16 | 2025-03-27SEMICONDUCTOR DEVICE INCLUDING SUPERLATTICE WITH O18 ENRICHED MONOLAYERS
#17 | 2025-03-27METHOD FOR MAKING A SEMICONDUCTOR DEVICE USING SUPERLATTICES WITH DIFFERENT NON-SEMICONDUCTOR THERMAL STABILITIES
#18 | 2025-02-06COMPLEMENTARY FIELD EFFECT TRANSISTOR (CFET) DEVICES INCLUDING SUPERLATTICE ISOLATION LAYER
#19 | 2025-02-06METHOD FOR MAKING COMPLEMENTARY FIELD EFFECT TRANSISTOR (CFET) DEVICES INCLUDING SUPERLATTICE ISOLATION LAYER
#20 | 2025-02-06METHOD FOR MAKING GATE-ALL-AROUND (GAA) DEVICE INCLUDING A SUPERLATTICE
#21 | 2025-01-02METHOD FOR MAKING SEMICONDUCTOR DEVICE INCLUDING SUPERLATTICE WITH OXYGEN AND CARBON MONOLAYERS
#22 | 2024-10-10Method for making semiconductor device including a superlattice and enriched silicon 28 epitaxial layer
#23 | 2024-06-13GATE-ALL-AROUND (GAA) DEVICE INCLUDING A SUPERLATTICE
#24 | 2024-06-13Method for making semiconductor device with selective etching of superlattice to accumulate non-semiconductor atoms
#25 | 2024-05-23SEMICONDUCTOR DEVICE INCLUDING A SUPERLATTICE AND ENRICHED SILICON 28 EPITAXIAL LAYER
#26 | 2024-02-22Method for making semiconductor device including superlattice with oxygen and carbon monolayers
#27 | 2023-12-21SEMICONDUCTOR DEVICES WITH EMBEDDED QUANTUM DOTS AND RELATED METHODS
#28 | 2023-12-21METHODS FOR MAKING SEMICONDUCTOR DEVICES WITH SUPERLATTICE AND EMBEDDED QUANTUM DOTS
#29 | 2023-12-07Method for making semiconductor device including a superlattice and enriched silicon 28 epitaxial layer
#30 | 2023-11-09Semiconductor device including superlattice with O18 enriched monolayers
#31 | 2023-05-04Method for making semiconductor device with selective etching of superlattice to accumulate non-semiconductor atoms
#32 | 2023-05-04Method for making semiconductor device with selective etching of superlattice to define etch stop layer
#33 | 2023-04-20Method for making gate-all-around (GAA) device including a superlattice
#34 | 2023-04-20Gate-all-around (GAA) device including a superlattice
#35 | 2022-12-01Method for making semiconductor device including superlattice with O18 enriched monolayers
#36 | 2022-12-01Semiconductor device including superlattice with Oenriched monolayers
#37 | 2022-11-03Semiconductor device including a superlattice and enriched silicon 28 epitaxial layer
#38 | 2022-10-27Method for making semiconductor device including a superlattice and enriched silicon 28 epitaxial layer
#39 | 2022-01-06Method for making semiconductor device including superlattice with oxygen and carbon monolayers
#40 | 2022-01-06Semiconductor device including superlattice with oxygen and carbon monolayers
#41 | 2022-01-06Method for making a semiconductor superlattices with different non-semiconductor thermal stabilities
#42 | 2021-01-21Method for making a varactor with a hyper-abrupt junction region including spaced-apart superlattices
#43 | 2021-01-21Method for making semiconductor devices with hyper-abrupt junction region including spaced-apart superlattices
#44 | 2021-01-21Semiconductor devices including hyper-abrupt junction region including spaced-apart superlattices and related methods
#45 | 2021-01-21Method for making a semiconductor device having a hyper-abrupt junction region including a superlattice
#46 | 2020-12-31Method for making superlattice structures with reduced defect densities
#47 | 2020-12-15Method for making a varactor with hyper-abrupt junction region including a superlattice
#48 | 2020-11-17Varactor with hyper-abrupt junction region including a superlattice
#49 | 2020-11-03Semiconductor devices including hyper-abrupt junction region including a superlattice
#50 | 2020-11-03Varactor with hyper-abrupt junction region including spaced-apart superlattices
#51 | 2020-05-21Semiconductor device including body contact dopant diffusion blocking superlattice having reduced contact resistance
#52 | 2020-05-21Method for making semiconductor device including source/drain dopant diffusion blocking superlattices to reduce contact resistance
#53 | 2020-05-21Method for making a FINFET including source and drain dopant diffusion blocking superlattices to reduce contact resistance
#54 | 2020-05-21Method for making a FINFET having reduced contact resistance
#55 | 2020-05-21Semiconductor device with metal-semiconductor contacts including oxygen insertion layer to constrain dopants and related methods
#56 | 2020-05-21Method for making semiconductor device including body contact dopant diffusion blocking superlattice to reduce contact resistance
#57 | 2020-04-30METHOD FOR MAKING A SEMICONDUCTOR DEVICE INCLUDING A SUPERLATTICE HAVING NITROGEN DIFFUSED THEREIN
#58 | 2020-03-17Method for making a semiconductor device having reduced contact resistance
#59 | 2020-03-05Method for making superlattice structures with reduced defect densities
#60 | 2020-03-05Semiconductor device including superlattice structures with reduced defect densities
#61 | 2020-03-03Semiconductor device including source/drain dopant diffusion blocking superlattices to reduce contact resistance
#62 | 2020-03-03FINFET including source and drain regions with dopant diffusion blocking superlattice layers to reduce contact resistance
#63 | 2019-09-12Method for making a semiconductor device including compound semiconductor materials and an impurity and point defect blocking superlattice
#64 | 2019-09-12Semiconductor device including compound semiconductor materials and an impurity and point defect blocking superlattice
#65 | 2019-06-20Method for making CMOS image sensor including superlattice to enhance infrared light absorption
#66 | 2019-04-30CMOS image sensor including superlattice to enhance infrared light absorption
#67 | 2018-10-23Method of making a semiconductor device with a buried insulating layer formed by annealing a superlattice
#68 | 2018-02-08Semiconductor device including a resonant tunneling diode structure with electron mean free path control layers
#69 | 2018-02-08Method for making a semiconductor device including a resonant tunneling diode structure having a superlattice
#70 | 2018-02-08Semiconductor device including resonant tunneling diode structure having a superlattice
#71 | 2018-02-08Method for making a semiconductor device including a resonant tunneling diode with electron mean free path control layers
#72 | 2011-08-11Multiple-wavelength opto-electronic device including a superlattice
#73 | 2010-10-28ELECTRONIC DEVICE INCLUDING AN ELECTRICALLY POLLED SUPERLATTICE AND RELATED METHODS
#74 | 2008-08-21Method for making a multiple-wavelength opto-electronic device including a superlattice
#75 | 2008-08-21Multiple-wavelength opto-electronic device including a superlattice
#76 | 2008-01-17SPINTRONIC DEVICES WITH CONSTRAINED SPINTRONIC DOPANT
#77 | 2007-10-11Methods of making spintronic devices with constrained spintronic dopant
#78 | 2007-08-23Method for making a semiconductor device comprising a lattice matching layer
#79 | 2007-08-23Semiconductor device comprising a lattice matching layer
#80 | 2007-08-16ELECTRONIC DEVICE INCLUDING A SELECTIVELY POLABLE SUPERLATTICE
#81 | 2007-07-19METHOD FOR MAKING AN ELECTRONIC DEVICE INCLUDING A SELECTIVELY POLABLE SUPERLATTICE
#82 | 2007-07-12Method for making an electronic device including a poled superlattice having a net electrical dipole moment
#83 | 2007-07-12ELECTRONIC DEVICE INCLUDING A POLED SUPERLATTICE HAVING A NET ELECTRICAL DIPOLE MOMENT
#84 | 2007-01-25Method for Making a Semiconductor Device Including a Channel with a Non-Semiconductor Layer Monolayer
#85 | 2007-01-18Semiconductor Device Including a Channel with a Non-Semiconductor Layer Monolayer
#86 | 2006-12-07METHOD FOR MAKING A SEMICONDUCTOR DEVICE INCLUDING A DOPANT BLOCKING SUPERLATTICE
#87 | 2006-10-05SEMICONDUCTOR DEVICE INCLUDING A DOPANT BLOCKING SUPERLATTICE
#88 | 2006-04-25Method for making semiconductor device including band-engineered superlattice
#89 | 2006-01-26Method for making a semiconductor device comprising a superlattice dielectric interface layer
#90 | 2006-01-19Semiconductor device comprising a superlattice dielectric interface layer
#91 | 2005-12-08Method for making a semiconductor device including band-engineered superlattice using intermediate annealing
#92 | 2005-10-25Semiconductor device including band-engineered superlattice
#93 | 2005-10-04Semiconductor device including band-engineered superlattice
#94 | 2005-08-25Semiconductor device including MOSFET having band-engineered superlattice
#95 | 2005-08-11Semiconductor device including a MOSFET having a band-engineered superlattice with a semiconductor cap layer providing a channel
#96 | 2005-08-11Method for making a semiconductor device including a MOSFET having a band-engineered superlattice with a semiconductor cap layer providing a channel
#97 | 2005-05-24Semiconductor device including MOSFET having band-engineered superlattice
#98 | 2005-05-10Semiconductor device including band-engineered superlattice
#99 | 2005-04-28Method for making a semiconductor device including band-engineered superlattice having 3/1-5/1 germanium layer structure
#100 | 2005-04-28Semiconductor device including band-engineered superlattice having 3/1-5/1 germanium layer structure
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