STMicroelectronics PVT LTD.

Dual port SRAM having reduced cell size and rectangular shape

Trigger circuit and method of using same

SRAM memory device and testing method thereof

Locally synchronous shared BIST architecture for testing embedded memories with asynchronous interfaces

Digital video encoder system, method, and non-transitory computer-readable medium for tracking object regions

Object tracking

Flip chip device having simplified routing

Bistable CML circuit

Object detection in an image

Current steering DAC with switched cascode output current source/sink

Circuit for glitchless switching between asynchronous clocks

Multiple output level shifter

System and method for object based parametric video coding

Clock recovery from data streams containing embedded reference clock values

Architecture for efficient usage of IO

Overlaying videos on a display device

Balanced sense amplifier for single ended bitline memory architecture

Base cell for engineering change order (ECO) implementation

Matrix structure oscillator

Pulse filtering module circuit, system, and method

Assistance in reset of data storage array

Switched charge storage element network

Non-scalable to scalable video converter

System and method for on-chip duty cycle measurement

Method and system for determining a macroblock partition for data transcoding

Compensated output buffer for improving slew control rate

Flexible on chip testing circuit for I/O's characterization

Architecture incorporating configurable controller for reducing on chip power leakage

System and method for fast re-locking of a phase locked loop circuit

Method and system for optimizing power consumption and reducing MIPS requirements for wireless communication

Biased sensing module

Self-timing read architecture for semiconductor memory and method for providing the same

Spread spectrum clock generation

Locally synchronous shared BIST architecture for testing embedded memories with asynchronous interfaces

Suppressing ringing in high speed CMOS output buffers driving transmission line load

Self programmable shared bist for testing multiple memories

Memory management module

Self-updating memory controller

Configurable I2C interface

High steps brushless DC (BLDC) motor

Binary decoders in electronic integrated circuits

Memory structure for optimized image processing

Programmable delay introducing circuit in self timed memory

Architecture for reducing leakage component in semiconductor devices

Low-voltage-to-high-voltage level converter for digital signals and related integrated circuit, system, and method

High speed, low power, low leakage read only memory

First-in first-out (FIFO) memory with multi-port functionality

Area efficient programmable frequency divider

Self timing write architecture for semiconductor memory and method for providing the same

Multiple embedded memories and testing components for the same

Latch-type sense amplifier

Boundary scan of integrated circuits

Dynamic power management in system on chips (SOC)

System for providing access of multiple data buffers to a data retaining and processing device

Built-in self-repairable memory

Content addressable memory architecture providing improved speed

Shared redundant memory architecture and memory system incorporating same

Method and device for testing configuration memory cells in programmable logic devices (PLDS)

Self test structure for interconnect and logic element testing in programmable devices

Area efficient memory architecture with decoder self test and debug capability

Configurable length first-in first-out memory

Rapid interconnect and logic testing of FPGA device

Area efficient shift / rotate system

Method and apparatus for providing compensation against temperature, process and supply voltage variation

Method and system for reducing power consumption in digital circuitry using charge redistribution circuits

Phase generator for introducing phase shift in a signal

Programmable frequency divider

Supply voltage identifier

Integrated circuit including at least one configurable logic cell capable of multiplication

N-bit constant adder/subtractor

Efficient content addressable memory array for classless inter-domain routing

Memory with reduced bitline leakage current and method for the same

Timing skew measurement system

Glitch free controlled ring oscillator and associated methods

Method and apparatus for multiplexing an integrated circuit pin

Minimal area integrated circuit implementation of a polyphase interpolation filter using coefficients symmetry

Configuration memory structure

Measurement of timing skew between two digital signals

LUT based multiplexers

Voltage tolerant protection circuit for input buffer

Memory architecture for increased speed and reduced power consumption

Pseudo true single phase clock latch with feedback mechanism

High performance interconnect architecture for field programmable gate arrays

Conversion device for performing a raster scan conversion between a JPEG decoder and an image memory

Macro-block level parallel video decoder

Turbo encoder and related methods

Logic entity with two outputs for efficient adder and other macro implementations

High performance adaptive load output buffer with fast switching of capacitive loads

Synchronous SRAM capable of faster read-modify-write operation

FPGA-based digital circuit for reducing readback time

One bit full adder with sum and carry outputs capable of independent functionalities

On-chip and at-speed tester for testing and characterization of different types of memories

Chua's circuit and it's use in a hyperchaotic circuit

Method for finding maximum volume and minimum cut in a network of interconnected nodes

On-chip storage memory for storing variable data bits

Automatic selection of an on-chip ancillary internal clock generator upon resetting a digital system

Boundary scan tester for logic devices

Output buffer providing multiple voltages