Inventor profile of:

Ashish Kumar

City:

Ranchi

Country:

India

Published Applications:

19

Last publication date:

2026-03-05

Top Assignees for applications by Ashish Kumar

The entities that hold a legal rights for patent applications filed by inventor Kumar Ashish:

Recent patent applications by Kumar Ashish

Ashish Kumar from Ranchi, IN has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2026-03-05
US20260065978A1
Physics

PROCESS AND TEMPERATURE COMPENSATED WORD LINE UNDERDRIVE SCHEME FOR SRAM

#2 | 2024-02-29
US20240071480A1
Physics

PROCESS AND TEMPERATURE COMPENSATED WORD LINE UNDERDRIVE SCHEME FOR SRAM

#3 | 2022-01-20
US20220020405A1
Physics

High speed SRAM using enhance wordline/global buffer drive

#4 | 2020-10-15
US20200327927A1
Physics

Reduced retention leakage SRAM

#5 | 2020-03-05
US20200075090A1
Physics

PULSED APPLICATION OF WORDLINE UNDERDRIVE (WLUD) FOR ENHANCING STABILITY OF STATIC RANDOM ACCESS MEMORY (SRAM) OPERATION IN A LOW SUPPLY VOLTAGE ENVIRONMENT

#6 | 2019-06-13
US20190182630A1
Electricity

Optimization of broadcast and multicast frame delivery in power-save mode

#7 | 2018-07-05
US20180190346A1
Physics

Method and apparatus for enhancing read stability of a static random access memory circuit in low voltage operation

#8 | 2017-11-02
US20170316820A1
Physics

Method and apparatus for enhancing read stability of a static random access memory circuit in low voltage operation

#9 | 2017-10-19
US20170301396A1
Physics

Temperature compensated read assist circuit for a static random access memory (SRAM)

#10 | 2017-06-20
US15132388
Physics

Circuit for generating a sense amplifier enable signal with variable timing

#11 | 2014-12-25
US20140376322A1
Physics

RETENTION OF DATA DURING STAND-BY MODE

#12 | 2014-09-25
US20140286116A1
Physics

Noise tolerant sense circuit

#13 | 2013-05-23
US20130128656A1
Physics

SRAM memory device and testing method thereof

#14 | 2011-02-03
US20110026309A1
Physics

Self-timed write boost for SRAM cell with self mode control

#15 | 2007-08-30
US20070200617A1
Electricity

Architecture for reducing leakage component in semiconductor devices

#16 | 2006-10-03
US10768962
-

Method and system for reducing power consumption in digital circuitry using charge redistribution circuits

#17 | 2006-09-14
US20060203536A1
Physics

Memory device with reduced leakage current

#18 | 2006-03-09
US20060050590A1
Physics

Logic device with reduced leakage current

#19 | 2005-05-17
US10684076
-

Sense amplifier with feedback-controlled bitline access

InventorID:

258932 ⎘