San Jose, California
United States
56
2014-05-01
53
2015-03-10
These are the the leading inventors for applications assigned to APLUS FLASH TECHNOLOGY, INC.:
APLUS FLASH TECHNOLOGY, INC. based in San Jose, US has been assigned the rights to these inventions. The list includes both Pending Applications and Patent Grants:
NVSRAM cells with voltage flash charger
#2 | 2014-05-01 ✅ Patent 8,971,113 granted on 2015-03-03Pseudo-8T NVSRAM cell with a charge-follower
#3 | 2014-05-01 ✅ Patent 8,929,136 granted on 2015-01-068T NVSRAM cell and cell operations
#4 | 2014-04-24 ✅ Patent 9,177,645 granted on 2015-11-0310T NVSRAM cell and cell operations
#5 | 2014-04-17 ✅ Patent 9,001,583 granted on 2015-04-07On-chip HV and LV capacitors acting as the second back-up supplies for NVSRAM auto-store operation
#6 | 2014-03-27 ✅ Patent 8,964,470 granted on 2015-02-24Method and architecture for improving defect detectability, coupling area, and flexibility of NVSRAM cells and arrays
#7 | 2014-02-20 ✅ Patent 9,177,644 granted on 2015-11-03Low-voltage fast-write PMOS NVSRAM cell
#8 | 2013-11-07LOW-VOLTAGE FAST-WRITE NVSRAM CELL
#9 | 2013-10-17 ✅ Patent 9,171,627 granted on 2015-10-27Non-boosting program inhibit scheme in NAND design
#10 | 2013-08-22Three-Dimensional Flash-Based Combo Memory and Logic Design
#11 | 2013-07-18 ✅ Patent 8,923,049 granted on 2014-12-301T1b and 2T2b flash-based, data-oriented EEPROM design
#12 | 2013-05-23 ✅ Patent 9,019,764 granted on 2015-04-28Low-voltage page buffer to be used in NVM design
#13 | 2012-08-02 ✅ Patent 8,582,363 granted on 2013-11-12Method and apparatus for management of over-erasure in NAND-based NOR-type flash memory
#14 | 2012-07-26One-Die Flotox-Based Combo Non-Volatile Memory
#15 | 2012-07-12 ✅ Patent 8,917,551 granted on 2014-12-23Flexible 2T-based fuzzy and certain matching arrays
#16 | 2012-02-23 ✅ Patent 8,345,481 granted on 2013-01-01NAND based NMOS NOR flash memory cell, a NAND based NMOS NOR flash memory array, and a method of forming a NAND based NMOS NOR flash memory array
#17 | 2012-01-05 ✅ Patent 8,455,923 granted on 2013-06-04Embedded NOR flash memory process with NAND cell and true logic compatible low voltage device
#18 | 2011-12-01 ✅ Patent 8,531,885 granted on 2013-09-10NAND-based 2T2b NOR flash array with a diode connection to cell's source node for size reduction using the least number of metal layers
#19 | 2011-11-03 ✅ Patent 8,559,232 granted on 2013-10-15DRAM-like NVM memory array and sense amplifier design for high temperature and high endurance operation
#20 | 2011-06-30 ✅ Patent 8,233,320 granted on 2012-07-31High speed high density NAND-based 2T-NOR flash memory design
#21 | 2011-06-30 ✅ Patent 8,462,553 granted on 2013-06-11Cell array for highly-scalable, byte-alterable, two-transistor FLOTOX EEPROM non-volatile memory
#22 | 2011-03-03 ✅ Patent 8,355,287 granted on 2013-01-15Method and apparatus for operation of a NAND-like dual charge retaining transistor NOR flash memory device
#23 | 2010-12-30 ✅ Patent 8,149,622 granted on 2012-04-03Memory system having NAND-based NOR and NAND flashes and SRAM integrated in one chip for hybrid data, code and cache storage
#24 | 2010-08-05 ✅ Patent 8,120,966 granted on 2012-02-21Method and apparatus for management of over-erasure in NAND-based NOR-type flash memory
#25 | 2010-05-20 ✅ Patent 8,335,108 granted on 2012-12-18Bit line gate transistor structure for a multilevel, dual-sided nonvolatile memory cell NAND flash array
#26 | 2009-12-24 ✅ Patent 8,289,775 granted on 2012-10-16Apparatus and method for inhibiting excess leakage current in unselected nonvolatile memory cells in an array
#27 | 2009-12-17 ✅ Patent 8,120,959 granted on 2012-02-21NAND string based NAND/NOR flash memory cell, array, and memory device having parallel bit lines and source lines, having a programmable select gating transistor, and circuits and methods for operating same
#28 | 2009-12-17 ✅ Patent 8,274,829 granted on 2012-09-25Row-decoder and source-decoder structures suitable for erase in unit of page, sector and chip of a NOR-type flash operating below +/− 10V BVDS
#29 | 2009-12-17 ✅ Patent 8,295,087 granted on 2012-10-23Row-decoder and select gate decoder structures suitable for flashed-based EEPROM operating below +/− 10v BVDS
#30 | 2009-11-12 ✅ Patent 8,072,811 granted on 2011-12-06NAND based NMOS NOR flash memory cell, a NAND based NMOS NOR flash memory array, and a method of forming a NAND based NMOS NOR flash memory array
#31 | 2009-08-13 ✅ Patent 8,472,251 granted on 2013-06-25Single-polycrystalline silicon electrically erasable and programmable nonvolatile memory device
#32 | 2009-07-30 ✅ Patent 8,331,150 granted on 2012-12-11Integrated SRAM and FLOTOX EEPROM memory device
#33 | 2008-10-16 ✅ Patent 7,688,612 granted on 2010-03-30Bit line structure for a multilevel, dual-sided nonvolatile memory cell array
#34 | 2008-09-18 ✅ Patent 7,830,713 granted on 2010-11-09Bit line gate transistor structure for a multilevel, dual-sided nonvolatile memory cell NAND flash array
#35 | 2008-08-28 ✅ Patent 7,855,912 granted on 2010-12-21Circuit and method for multiple-level programming, reading, and erasing dual-sided nonvolatile memory cell
#36 | 2007-06-14 ✅ Patent 7,349,257 granted on 2008-03-25Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations
#37 | 2007-04-05 ✅ Patent 7,339,824 granted on 2008-03-04Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations
#38 | 2007-03-01 ✅ Patent 7,283,401 granted on 2007-10-16Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout
#39 | 2006-10-19 ✅ Patent 7,324,384 granted on 2008-01-29Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout
#40 | 2006-08-10 ✅ Patent 7,372,736 granted on 2008-05-13Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout
#41 | 2006-08-03 ✅ Patent 7,289,366 granted on 2007-10-30Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout
#42 | 2006-06-29 ✅ Patent 7,369,438 granted on 2008-05-06Combo memory design and technology for multiple-function java card, sim-card, bio-passport and bio-id card applications
#43 | 2006-06-20 ✅ Patent 7,064,978 granted on 2006-06-20Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout
#44 | 2006-06-08 ✅ Patent 7,087,953 granted on 2006-08-08Unified non-volatile memory device and method for integrating NOR and NAND-type flash memory and EEPROM device on a single substrate
#45 | 2006-06-01 ✅ Patent 7,177,190 granted on 2007-02-13Combination nonvolatile integrated memory system using a universal technology most suitable for high-density, high-flexibility and high-security sim-card, smart-card and e-passport applications
#46 | 2006-02-02 ✅ Patent 7,164,608 granted on 2007-01-16NVRAM memory cell architecture that integrates conventional SRAM and flash cells
#47 | 2005-08-25 ✅ Patent 7,149,120 granted on 2006-12-12Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations
#48 | 2005-07-28 ✅ Patent 7,110,302 granted on 2006-09-19Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout
#49 | 2005-06-30 ✅ Patent 7,154,783 granted on 2006-12-26Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations
#50 | 2005-06-23 ✅ Patent 7,102,929 granted on 2006-09-05Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout
#51 | 2005-06-16 ✅ Patent 7,120,064 granted on 2006-10-10Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout
#52 | 2005-06-09 ✅ Patent 7,075,826 granted on 2006-07-11Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout
#53 | 2005-05-10 ✅ Patent 6,891,221 granted on 2005-05-10Array architecture and process flow of nonvolatile memory devices for mass storage applications
#54 | 2005-03-01 ✅ Patent 6,862,223 granted on 2005-03-01MONOLITHIC, COMBO NONVOLATILE MEMORY ALLOWING BYTE, PAGE AND BLOCK WRITE WITH NO DISTURB AND DIVIDED-WELL IN THE CELL ARRAY USING A UNIFIED CELL STRUCTURE AND TECHNOLOGY WITH A NEW SCHEME OF DECODER AND LAYOUT
#55 | 2005-02-01 ✅ Patent 6,850,438 granted on 2005-02-01Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations
#56 | 2005-01-04 ✅ Patent 6,839,278 granted on 2005-01-04Highly-integrated flash memory and mask ROM array architecture
Also check out Aplus Flash Technology, Inc's (San Jose, United States) applicant profile with 7 patent applications submitted.
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