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Inventor profile of:

Peter Lee

City:

Saratoga, California

Country:

United States

Published Applications:

5

Last publication date:

2008-08-28

Top Assignees for applications by Peter Lee

The entities that hold a legal rights for patent applications filed by inventor Lee Peter:

  • APLUS FLASH TECHNOLOGY, INC. 4 San Jose, CA United States

Recent patent applications by Lee Peter

Peter Lee from Saratoga, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2008-08-28
US20080205141A1
Electricity

Circuit and method for multiple-level programming, reading, and erasing dual-sided nonvolatile memory cell

#2 | 2008-08-28
US20080205140A1
Electricity

Bit line structure for a multilevel, dual-sided nonvolatile memory cell array

#3 | 2006-02-02
US20060023503A1
Physics

NVRAM memory cell architecture that integrates conventional SRAM and flash cells

#4 | 2005-06-16
US20050128805A1
Electricity

Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout

#5 | 2005-01-04
US10353584
-

Highly-integrated flash memory and mask ROM array architecture

InventorID:

4240147 ⎘

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