Santa Clara, California
United States
62
2025-09-16
56
2025-09-16
These are the the leading inventors for applications assigned to PDF Solutions, Inc.:
PDF Solutions, Inc. based in Santa Clara, US has been assigned the rights to these inventions. The list includes both Pending Applications and Patent Grants:
Embedded system to characterize BTI degradation effects in MOSFETs
#2 | 2025-05-01Sequenced Approach for Determining Wafer Path Quality
#3 | 2024-10-31Predicting Equipment Fail Mode from Process Trace
#4 | 2024-10-03 ✅ Patent 12,429,520 granted on 2025-09-30SYSTEMS, DEVICES, AND METHODS FOR PERFORMING A NON-CONTACT ELECTRICAL MEASUREMENT ON A CELL, NON-CONTACT ELECTRICAL MEASUREMENT CELL VEHICLE, CHIP, WAFER, DIE, OR LOGIC BLOCK
#5 | 2024-09-12 ✅ Patent 12,431,333 granted on 2025-09-30SYSTEMS, DEVICES, AND METHODS FOR ALIGNING A PARTICLE BEAM AND PERFORMING A NON-CONTACT ELECTRICAL MEASUREMENT ON A CELL AND/OR NON-CONTACT ELECTRICAL MEASUREMENT CELL VEHICLE USING A REGISTRATION CELL
#6 | 2024-06-06Time-Series Segmentation and Anomaly Detection
#7 | 2024-04-18Evaluating a Surface Microstructure
#8 | 2023-11-23 ✅ Patent 12,229,945 granted on 2025-02-18Wafer bin map based root cause analysis
#9 | 2023-11-09 ✅ Patent 12,038,476 granted on 2024-07-16Systems, devices, and methods for performing a non-contact electrical measurement on a cell, non-contact electrical measurement cell vehicle, chip, wafer, die, or logic block
#10 | 2023-09-07 ✅ Patent 12,020,897 granted on 2024-06-25Systems, devices, and methods for aligning a particle beam and performing a non-contact electrical measurement on a cell and/or non-contact electrical measurement cell vehicle using a registration cell
#11 | 2022-11-17 ✅ Patent 11,668,746 granted on 2023-06-06Systems, devices, and methods for performing a non-contact electrical measurement on a cell, non-contact electrical measurement cell vehicle, chip, wafer, die, or logic block
#12 | 2022-10-20 ✅ Patent 11,605,526 granted on 2023-03-14Systems, devices, and methods for aligning a particle beam and performing a non-contact electrical measurement on a cell and/or non-contact electrical measurement cell vehicle using a registration cell
#13 | 2022-10-13 ✅ Patent 11,775,714 granted on 2023-10-03Rational decision-making tool for semiconductor processes
#14 | 2022-03-03Sequenced Approach For Determining Wafer Path Quality
#15 | 2022-02-10 ✅ Patent 11,640,160 granted on 2023-05-02Pattern-enhanced spatial correlation of test structures to die level responses
#16 | 2022-01-27 ✅ Patent 11,687,439 granted on 2023-06-27Automatic window generation for process trace
#17 | 2022-01-27 ✅ Patent 11,640,328 granted on 2023-05-02Predicting equipment fail mode from process trace
#18 | 2021-11-04 ✅ Patent 11,763,446 granted on 2023-09-19Wafer bin map based root cause analysis
#19 | 2021-10-28 ✅ Patent 11,972,552 granted on 2024-04-30Abnormal wafer image classification
#20 | 2021-09-23Rational Decision-Making Tool for Semiconductor Processes
#21 | 2021-09-09 ✅ Patent 11,328,108 granted on 2022-05-10Predicting die susceptible to early lifetime failure
#22 | 2021-07-27 ✅ Patent 11,075,194 granted on 2021-07-27IC with test structures and E-beam pads embedded within a contiguous standard cell area
#23 | 2021-05-13 ✅ Patent 12,038,802 granted on 2024-07-16Collaborative learning model for semiconductor applications
#24 | 2021-04-22 ✅ Patent 11,972,987 granted on 2024-04-30Die level product modeling without die level input data
#25 | 2021-04-22 ✅ Patent 12,223,012 granted on 2025-02-11Machine learning variable selection and root cause discovery by cumulative prediction
#26 | 2021-04-08 ✅ Patent 11,609,812 granted on 2023-03-21Anomalous equipment trace detection and classification
#27 | 2021-04-01 ✅ Patent 11,328,899 granted on 2022-05-10Methods for aligning a particle beam and performing a non-contact electrical measurement on a cell using a registration cell
#28 | 2021-04-01 ✅ Patent 11,340,293 granted on 2022-05-24Methods for performing a non-contact electrical measurement on a cell, chip, wafer, die, or logic block
#29 | 2020-12-01 ✅ Patent 10,854,522 granted on 2020-12-01Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-side short or leakage, at least one corner short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective tip-to-side short, corner short, and via open test areas
#30 | 2020-10-13 ✅ Patent 10,803,221 granted on 2020-10-13Snap-to valid pattern system and method
#31 | 2020-09-15 ✅ Patent 10,777,472 granted on 2020-09-15IC with test structures embedded within a contiguous standard cell area
#32 | 2020-09-08 ✅ Patent 10,768,222 granted on 2020-09-08Method and apparatus for direct testing and characterization of a three dimensional semiconductor memory structure
#33 | 2020-06-09 ✅ Patent 10,679,723 granted on 2020-06-09Direct memory characterization using periphery transistors
#34 | 2020-05-05 ✅ Patent 10,643,735 granted on 2020-05-05Passive array test structure for cross-point memory characterization
#35 | 2020-05-05 ✅ Patent 10,641,804 granted on 2020-05-05Method for applying charge-based-capacitance-measurement with switches using only NMOS or only PMOS transistors
#36 | 2020-04-16 ✅ Patent 10,897,814 granted on 2021-01-19Characterization vehicles for printed circuit board and system design
#37 | 2020-03-17 ✅ Patent 10,593,604 granted on 2020-03-17Process for making semiconductor dies, chips, and wafers using in-line measurements obtained from DOEs of NCEM-enabled fill cells
#38 | 2020-02-18 ✅ Patent 10,565,344 granted on 2020-02-18Standard cell design conformance using boolean assertions
#39 | 2019-10-17 ✅ Patent 10,517,169 granted on 2019-12-24Characterization vehicles for printed circuit board and system design
#40 | 2019-10-03 ✅ Patent 10,777,470 granted on 2020-09-15Selective inclusion/exclusion of semiconductor chips in accelerated failure tests
#41 | 2019-09-12 ✅ Patent 11,029,359 granted on 2021-06-08Failure detection and classsification using sensor data and/or measurement data
#42 | 2019-09-10 ✅ Patent 10,410,735 granted on 2019-09-10Direct access memory characterization vehicle
#43 | 2019-05-16 ✅ Patent 10,656,204 granted on 2020-05-19Failure detection for wire bonding in semiconductors
#44 | 2019-05-14 ✅ Patent 10,290,552 granted on 2019-05-14Methods for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one via-chamfer short or leakage, and at least one corner short or leakage, where such measurements are obtained from cells with respective tip-to-tip short, via-chamfer short, and corner short test areas, using a charged particle-beam inspector with beam deflection to account for motion of the stage
#45 | 2019-04-23 ✅ Patent 10,269,786 granted on 2019-04-23Integrated circuit containing first and second DOEs of standard Cell Compatible, NCEM-enabled Fill Cells, with the first DOE including tip-to-side short configured fill cells, and the second DOE including corner short configured fill cells
#46 | 2019-04-16 ✅ Patent 10,263,011 granted on 2019-04-16Process for making ICs from standard logic cells that utilize TS cut mask(s) and avoid DFM problems caused by closely spaced gate contacts and TSCUT jogs
#47 | 2019-02-28 ✅ Patent 11,022,642 granted on 2021-06-01Semiconductor yield prediction
#48 | 2019-02-19 ✅ Patent 10,211,111 granted on 2019-02-19Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one corner short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, tip-to-side sort, and corner short test areas
#49 | 2019-02-19 ✅ Patent 10,211,112 granted on 2019-02-19Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one side-to-side short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, tip-to-side short, and side-to-side short test areas
#50 | 2019-02-05 ✅ Patent 10,199,294 granted on 2019-02-05Method for processing a semiconductor wafer using non-contact electrical measurements indicative of a least one side-to-side short or leakage, at least one via-chamfer short or leakage, and at least one corner short or leakage, where such measurements are obtained from cells with respective side-to-side short, via-chamfer short, and corner short test areas, using a charged particle-beam inspector with beam deflection to account for motion of the stage
#51 | 2019-02-05 ✅ Patent 10,199,290 granted on 2019-02-05Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one side-to-side short or leakage, where such measurements are obtained from cells with respective tip-to-tip short, tip-to-side short, and side-to-side short test areas, using a charged particle-beam inspector with beam deflection to account for motion of the stage
#52 | 2019-02-05 ✅ Patent 10,199,289 granted on 2019-02-05Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one chamfer short or leakage, at least one corner short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective chamfer short, corner short, and via open test areas
#53 | 2019-02-05 ✅ Patent 10,199,288 granted on 2019-02-05Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one side-to-side short or leakage, at least one corner short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective side-to-side short, corner short, and via open test areas
#54 | 2019-02-05 ✅ Patent 10,199,287 granted on 2019-02-05Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-side short or leakage, at least one chamfer short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective tip-to-side short, chamfer short, and via open test areas
#55 | 2019-02-05 ✅ Patent 10,199,286 granted on 2019-02-05Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-side short or leakage, at least one chamfer short or leakage, and at least one corner short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-side short, chamfer short, and corner short test areas
#56 | 2019-02-05 ✅ Patent 10,199,285 granted on 2019-02-05Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one side-to-side short or leakages, and at least one via respective tip-to-tip short, side-to-side short, and via open test areas
#57 | 2019-02-05 ✅ Patent 10,199,293 granted on 2019-02-05Method for processing a semiconductor water using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one side-to-side short or leakage, and at least one chamfer short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, side to side short, and chamfer short test areas
#58 | 2019-02-05 ✅ Patent 10,199,284 granted on 2019-02-05Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one chamfer short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, tip-to-side short, and chamfer short test areas
#59 | 2019-02-05 ✅ Patent 10,199,283 granted on 2019-02-05Method for processing a semiconductor wager using non-contact electrical measurements indicative of a resistance through a stitch, where such measurements are obtained by scanning a pad comprised of at least three parallel conductive stripes using a moving stage with beam deflection to account for motion of the stage
#60 | 2018-12-13 ✅ Patent 10,734,293 granted on 2020-08-04Process control techniques for semiconductor manufacturing processes
#61 | 2018-12-13 ✅ Patent 11,029,673 granted on 2021-06-08Generating robust machine learning predictions for semiconductor manufacturing processes
#62 | 2018-10-09 ✅ Patent 10,096,378 granted on 2018-10-09On-chip capacitance measurement for memory characterization vehicle
Also check out PDF Solutions, Inc.'s (Santa Clara, United States) applicant profile with 35 patent applications submitted.
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