Ventana Micro Systems Inc.

Physical address proxy reuse management

Processor that mitigates side channel attacks by preventing cache memory state from being affected by a missing load operation by inhibiting or canceling a fill request of the load operation if an older load generates a need for an architectural exception

Physical address proxy (PAP) residency determination for reduction of PAP reuse

Microprocessor that performs partial fallback abort processing of multi-fetch block macro-op cache entries

Prediction unit that predicts successor fetch block start address of multi-fetch block macro-op cache entry

Microprocessor that allows same-fetch block start address co-residence of unrolled loop multi-fetch block macro-op cache entry and loop body macro-op cache entry used to build same

Microprocessor that builds multi-fetch block macro-op cache entries in two-stage process

Microprocessor that builds consistent loop iteration count unrolled loop multi-fetch block macro-op cache entries

Using physical address proxies to accomplish penalty-less processing of load/store instructions whose data straddles cache line address boundaries

Microprocessor that performs mid-macro-op cache entry restart abort processing

Microprocessor that builds inconsistent loop that iteration count unrolled loop multi-fetch block macro-op cache entries

Microprocessor that extends sequential multi-fetch block macro-op cache entries

Prediction unit with first predictor that provides a hashed fetch address of a current fetch block to its own input and to a second predictor that uses it to predict the fetch address of a next fetch block

Virtually-indexed cache coherency using physical address proxies

Store-to-load forwarding correctness checks using physical address proxies stored in load queue entries

Prediction unit that predicts branch history update information produced by multi-fetch block macro-op cache entry

Microprocessor that builds sequential multi-fetch block macro-op cache entries

Microprocessor that performs selective multi-fetch block macro-op cache entry invalidation

Store-to-load forwarding correctness checks at store instruction commit

Unforwardable load instruction re-execution eligibility based on cache update by identified store instruction

Performance and power efficient processor when switching between fetching from decoded and non-decoded instruction sources

Macro-op cache data entry pointers distributed as initial pointers held in tag array and next pointers held in data array for efficient and performant variable length macro-op cache entries

Microprocessor with branch target buffer whose entries include fetch block hotness counters used for selective filtering of macro-op cache allocations

POWER MANAGEMENT OF DEVICES WITH DIFFERENTIATED POWER SCALING BASED ON RELATIVE POWER BENEFIT ESTIMATION

Using physical address proxies to handle synonyms when writing store data to a virtually-indexed cache

Processor that prevents speculative execution across translation context change boundaries to mitigate side channel attacks

Branch target buffer miss handling

METHOD AND APPARATUS FOR DESKEWING DIE TO DIE COMMUNICATION BETWEEN SYSTEM ON CHIP DEVICES

Microprocessor including a decode unit that performs pre-execution of load constant micro-operations

Prediction unit that provides a fetch block descriptor each clock cycle

Prediction unit with first predictor that provides a hashed fetch address of a current fetch block to its own input and to a second predictor that uses it to predict the fetch address of a next fetch block

Dynamically foldable and unfoldable instruction fetch pipeline

Branch target buffer that stores predicted set index and predicted way number of instruction cache

Folded instruction fetch pipeline

Single cycle predictor

Microprocessor with prediction unit pipeline that provides a next fetch address at a rate of one per clock cycle

Microprocessor that prevents store-to-load forwarding between different translation contexts

Physically-tagged data cache memory that uses translation context to reduce likelihood that entries allocated during execution under one translation context are accessible during execution under another translation context

Translation lookaside buffer consistency directory for use with virtually-indexed virtually-tagged first level data cache that holds page table permissions

Conditioning store-to-load forwarding (STLF) on past observations of STLF propriety

Thwarting store-to-load forwarding side channel attacks by pre-forwarding matching of physical address proxies and/or permission checking

Generational physical address proxies

Virtually-indexed cache coherency using physical address proxies

Microprocessor that prevents same address load-load ordering violations

Using physical address proxies to handle synonyms when writing store data to a virtually-indexed cache

Using physical address proxies to accomplish penalty-less processing of load/store instructions whose data straddles cache line address boundaries

Store-to-load forwarding correctness checks using physical address proxies stored in load queue entries

Write combining using physical address proxies stored in a write combine buffer

Unforwardable load instruction re-execution eligibility based on cache update by identified store instruction

Physical address proxy (PAP) residency determination for reduction of PAP reuse

Microprocessor that prevents same address load-load ordering violations using physical address proxies

Physical address proxy reuse management

Store-to-load forwarding correctness checks at store instruction commit

Store-to-load forwarding using physical address proxies to identify candidate set of store queue entries

Processor that mitigates side channel attacks by refraining from allocating an entry in a data TLB for a missing load address when the load address misses both in a data cache memory and in the data TLB and the load address specifies a location without a valid address translation or without permission to read from the location

Processor that mitigates side channel attacks by prevents cache line data implicated by a missing load address from being filled into a data cache memory when the load address specifies a location with no valid address translation or no permission to read from the location

Processor that mitigates side channel attacks by providing random load data as a result of execution of a load operation that does not have permission to access a load address

Processor that mitigates side channel attacks by preventing cache memory state from being affected by a missing load operation by inhibiting or canceling a fill request of the load operation if an older load generates a need for an architectural exception

Processor that mitigates side channel attacks by preventing all dependent instructions from consuming architectural register result produced by instruction that causes a need for an architectural exception

Processor that mitigates side channel attacks by expeditiously initiating flushing of instructions dependent upon a load instruction that causes a need for an architectural exception

Virtually-tagged data cache memory that uses translation context to make entries allocated during execution under one translation context inaccessible during execution under another translation context

Microprocessor that conditions store-to-load forwarding on circumstances associated with a translation context update

Processor that prevents speculative execution across translation context change boundaries to mitigate side channel attacks

Microprocessor core with a store dependence predictor accessed using a translation context

Microprocessor that prevents store-to-load forwarding between different translation contexts