Michael N. Michael

Microprocessor that performs partial fallback abort processing of multi-fetch block macro-op cache entries

Prediction unit that predicts successor fetch block start address of multi-fetch block macro-op cache entry

Microprocessor that allows same-fetch block start address co-residence of unrolled loop multi-fetch block macro-op cache entry and loop body macro-op cache entry used to build same

Microprocessor that builds multi-fetch block macro-op cache entries in two-stage process

Microprocessor that builds consistent loop iteration count unrolled loop multi-fetch block macro-op cache entries

Microprocessor that performs mid-macro-op cache entry restart abort processing

Microprocessor that builds inconsistent loop that iteration count unrolled loop multi-fetch block macro-op cache entries

Microprocessor that extends sequential multi-fetch block macro-op cache entries

Prediction unit with first predictor that provides a hashed fetch address of a current fetch block to its own input and to a second predictor that uses it to predict the fetch address of a next fetch block

Prediction unit that predicts branch history update information produced by multi-fetch block macro-op cache entry

Microprocessor that builds sequential multi-fetch block macro-op cache entries

Microprocessor that performs selective multi-fetch block macro-op cache entry invalidation

Performance and power efficient processor when switching between fetching from decoded and non-decoded instruction sources

Macro-op cache data entry pointers distributed as initial pointers held in tag array and next pointers held in data array for efficient and performant variable length macro-op cache entries

Microprocessor with branch target buffer whose entries include fetch block hotness counters used for selective filtering of macro-op cache allocations

Branch target buffer miss handling

Prediction unit that provides a fetch block descriptor each clock cycle

Prediction unit with first predictor that provides a hashed fetch address of a current fetch block to its own input and to a second predictor that uses it to predict the fetch address of a next fetch block

Dynamically foldable and unfoldable instruction fetch pipeline

Branch target buffer that stores predicted set index and predicted way number of instruction cache

Folded instruction fetch pipeline

Single cycle predictor

Microprocessor with prediction unit pipeline that provides a next fetch address at a rate of one per clock cycle