San Jose, California
United States
25
2008-11-04
25
2008-11-04
These are the the leading inventors for applications assigned to Inapac Technology, Inc:
Inapac Technology, Inc based in San Jose, US has been assigned the rights to these inventions. The list includes both Pending Applications and Patent Grants:
Integrated circuit testing module including address generator
#2 | 2008-04-29 ✅ Patent 7,365,557 granted on 2008-04-29Integrated circuit testing module including data generator
#3 | 2008-04-17 ✅ Patent 7,466,603 granted on 2008-12-16Memory accessing circuit system
#4 | 2008-03-13 ✅ Patent 7,443,188 granted on 2008-10-28Electronic device having an interface supported testing mode
#5 | 2007-09-11 ✅ Patent 7,269,524 granted on 2007-09-11Delay lock loop delay adjusting method and apparatus
#6 | 2007-07-19 ✅ Patent 7,370,256 granted on 2008-05-06Integrated circuit testing module including data compression
#7 | 2007-04-26 ✅ Patent 7,404,117 granted on 2008-07-22Component testing and recovery
#8 | 2007-01-18 ✅ Patent 7,466,160 granted on 2008-12-16Shared memory bus architecture for system with processor and memory units
#9 | 2007-01-02 ✅ Patent 7,157,940 granted on 2007-01-02System and methods for a high-speed dynamic data bus
#10 | 2006-12-14 ✅ Patent 7,309,999 granted on 2007-12-18Electronic device having an interface supported testing mode
#11 | 2006-11-21 ✅ Patent 7,139,945 granted on 2006-11-21Chip testing within a multi-chip semiconductor package
#12 | 2006-11-09 ✅ Patent 7,307,442 granted on 2007-12-11Integrated circuit test array including test module
#13 | 2006-11-07 ✅ Patent 7,133,798 granted on 2006-11-07Monitoring signals between two integrated circuit devices within a single package
#14 | 2006-10-19 ✅ Patent 7,310,000 granted on 2007-12-18Integrated circuit testing module including command driver
#15 | 2006-09-05 ✅ Patent 7,103,815 granted on 2006-09-05Testing of integrated circuit devices
#16 | 2006-07-13 ✅ Patent 7,245,141 granted on 2007-07-17Shared bond pad for testing a memory within a packaged semiconductor device
#17 | 2006-07-06 ✅ Patent 7,265,570 granted on 2007-09-04Integrated circuit testing module
#18 | 2006-06-13 ✅ Patent 7,061,263 granted on 2006-06-13Layout and use of bond pads and probe pads for testing of integrated circuits devices
#19 | 2006-02-28 ✅ Patent 7,006,940 granted on 2006-02-28Set up for a first integrated circuit chip to allow for testing of a co-packaged second integrated circuit chip
#20 | 2006-02-07 ✅ Patent 6,996,652 granted on 2006-02-07High-speed segmented data bus architecture
#21 | 2005-12-29 ✅ Patent 7,444,575 granted on 2008-10-28Architecture and method for testing of an integrated circuit device
#22 | 2005-09-15 ✅ Patent 7,259,582 granted on 2007-08-21Bonding pads for testing of a semiconductor device
#23 | 2005-07-28 ✅ Patent 7,313,740 granted on 2007-12-25Internally generating patterns for testing in an integrated circuit device
#24 | 2005-04-19 ✅ Patent 6,882,171 granted on 2005-04-19Bonding pads for testing of a semiconductor device
#25 | 2005-02-03 ✅ Patent 7,240,254 granted on 2007-07-03Multiple power levels for a chip within a multi-chip semiconductor package
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