Adrian E. Ong

CONTROLLER TO DETECT MALFUNCTIONING ADDRESS OF MEMORY DEVICE

Controller to detect malfunctioning address of memory device

ISOLATING ELECTRIC PATHS IN SEMICONDUCTOR DEVICE PACKAGES

Controller to detect malfunctioning address of memory device

Controller to detect malfunctioning address of memory device

MRAM architecture with multiplexed sense amplifiers and direct write through buffers

Vertical selector stt-MRAM architecture

Vertical selector STT-MRAM architecture

Controller to detect malfunctioning address of memory device

Controller to detect malfunctioning address of memory device

Ferroelectric memory array with hierarchical plate-line architecture

Testing fuse configurations in semiconductor devices

Controller to detect malfunctioning address of memory device

Isolating electric paths in semiconductor device packages

Vertical Thyristor Memory Array and Memory Array Tile Therefor

DDR Controller for Thyristor Memory Cell Arrays

Memory disturb recovery scheme for cross-point memory arrays

Controller to detect malfunctioning address of memory device

Testing fuse configurations in semiconductor devices

Memory array having segmented row addressed page registers

Memory device that supports multiple memory configurations

Controller to detect malfunctioning address of memory device

Method and system for providing a smart memory architecture

Controller to detect malfunctioning address of memory device

Integrated circuit testing

Controller to detect malfunctioning address of memory device

Adaptive dual voltage write driver with dummy resistive path tracking

Testing fuse configurations in semiconductor devices

Architecture for magnetic memories including magnetic tunneling junctions using spin-orbit interaction based switching

Programmable memory repair scheme

Voltage assisted STT-MRAM writing scheme

METHOD AND SYSTEM FOR PROVIDING A SMART MEMORY ARCHITECTURE

Method and design for high performance non-volatile memory

Sense amplifier circuitry for resistive type memory

Architecture, system and method for testing resistive type memory

Controller to detect malfunctioning address of memory device

ARCHITECTURE AND METHOD FOR REMOTE MEMORY SYSTEM DIAGNOSTIC AND OPTIMIZATION

Integrated circuit testing module including signal shaping interface

Multi-cell per memory-bit circuit and method

Parallel memory error detection and correction

Multi-supply symmetric driver circuit and timing method

Memory write error correction circuit

Non-volatile static ram cell circuit and timing method

Dynamic multistate memory write driver

Pseudo page mode memory architecture and method

Testing fuse configurations in semiconductor devices

Method and system for providing a magnetic field aligned spin transfer torque random access memory

Integrated circuit testing module including signal shaping interface

Processor-memory unit for use in system-in-package and system-in-module devices

METHOD AND SYSTEM FOR PROVIDING A HIGH DENSITY MEMORY CELL FOR SPIN TRANSFER TORQUE RANDOM ACCESS MEMORY

Method and system for providing a hierarchical data path for spin transfer torque random access memory

Differential read and write architecture

Programmable memory repair scheme

Processor-memory unit for use in system-in-package and system-in-module devices

Programmable memory repair scheme

Testing fuse configurations in semiconductor devices

Integrated circuit testing module including address generator

Integrated circuit testing module including data generator

Memory accessing circuit system

Delay lock loop delay adjusting method and apparatus

Electronic device having an interface supported testing mode

Memory device including multiplexed inputs

Isolating electric paths in semiconductor device packages

Integrated circuit testing module including data compression

Testing and recovery in a multilayer device

Component testing and recovery

Integrated circuit testing module including signal shaping interface

Integrated circuit testing module configured for set-up and hold time testing

Shared memory bus architecture for system with processor and memory units

System and methods for a high-speed dynamic data bus

Electronic device having an interface supported testing mode

Chip testing within a multi-chip semiconductor package

Integrated circuit test array including test module

Monitoring signals between two integrated circuit devices within a single package

Integrated circuit testing module including command driver

Testing of integrated circuit devices

Shared bond pad for testing a memory within a packaged semiconductor device

Integrated circuit testing module

Layout and use of bond pads and probe pads for testing of integrated circuits devices

Set up for a first integrated circuit chip to allow for testing of a co-packaged second integrated circuit chip

High-speed segmented data bus architecture

Architecture and method for testing of an integrated circuit device

Bonding pads for testing of a semiconductor device

Internally generating patterns for testing in an integrated circuit device

Bonding pads for testing of a semiconductor device

Multiple power levels for a chip within a multi-chip semiconductor package

Method and apparatus for checking the resistance of programmable elements