SiFive, Inc.

Window-based control for instruction issue in an out-of-order processor

ADDRESS BOUNDARY FUNCTIONS FOR PHYSICAL AND LOCALIZED ADDRESSES

Translation lookaside buffer probing prevention

CACHE REPLACEMENT POLICY STATE STRUCTURE WITH EXTRA STATES FOR PREFETCH AND NON-TEMPORAL LOADS

SYSTEMS AND METHODS FOR CLOCK GATING

Determining an Error Handling Mode

DEPENDENCY TRACKING AND CHAINING FOR VECTOR INSTRUCTIONS

Bundling and dynamic allocation of register blocks for vector instructions

INTEGRATED CIRCUIT GENERATION WITH IMPROVED INTERCONNECT

STORE-TO-LOAD FORWARDING FOR PROCESSOR PIPELINES

Debug In System On A Chip With Securely Partitioned Memory Space

Processor Crash Analysis Using Register Sampling

Error Management In System On A Chip With Securely Partitioned Memory Space

Vector Instruction Processing After Primary Decode

Address Range Encoding in System on a Chip with Securely Partitioned Memory Space

Macro-Op Fusion for Pipelined Architectures

Address boundary functions for physical and localized addresses

Making Circuitry Having An Attribute

Processing for vector load or store micro-operation with inactive mask elements

Tracking of store operations

Concurrent support for multiple cache inclusivity schemes using low priority evict operations

Debug Trace Circuitry Configured to Generate a Record Including an Address Pair and a Counter Value

Selective Transfer of Data Including a Priority Byte

Orderability of operations

Transmitting a response with a request and state information about the request

Downgrading a permission associated with data stored in a cache

Eviction operations based on eviction message types of different priorities

Speculative Request Indicator in Request Message

Prefetching Cache Blocks Based on an Address for a Group and a Bit Field

Cache Coherency State Request Vector Encoding and Use Thereof

DATA STORAGE IN NON-INCLUSIVE CACHE

Relative age tracking for entries in a buffer

SELECTABLE GRANULARITY PERFORMANCE MONITOR

Re-triggering wake-up to handle time skew between scalar and vector sides

Out-of-order vector iota calculations

Using renamed registers to support multiple vset{i}vl{i} instructions

Stalling issue queue entries until consecutive allocated entries are available for segmented stores

Vector Load Store Operations in a Vector Pipeline Using a Single Operation in a Load Store Unit

Transfer Buffer Between a Scalar Pipeline and Vector Pipeline

Stateful Vector Group Permutation with Storage Reuse

Flexible Power Management Interface

CONFIGURABLE INTERCONNECT ADDRESS REMAPPER WITH EVENT RECOGNITION

Predicting a Vector Length Associated with a Configuration Instruction

Selecting an Output as a System Output Responsive to an Indication of an Error

Vector Instruction Cracking After Scalar Dispatch

ATOMIC MEMORY OPERATIONS FOR ADDRESS TRANSLATION

Trace encoder with event filter

Fusion with Destructive Instructions

Supporting Multiple Vector Lengths with Configurable Vector Register File

EFFICIENT PROCESSING OF MASKED MEMORY ACCESSES

TRANSLATION LOOKASIDE BUFFER (TLB) PREFETCHER WITH MULTI- LEVEL TLB PREFETCHES AND FEEDBACK ARCHITECTURE

Load-store pipeline selection for vectors

Memory protection for vector operations

Memory protection for gather-scatter operations

REGISTER RENAMING FOR POWER CONSERVATION

Integrated Circuit Generation Using an Integrated Circuit Shell

Logging Guest Physical Address for Memory Access Faults

Selectable and hierarchical power management

VIRTUALIZED CACHES