Berkeley, California
United States
25
2026-03-12
The entities that hold a legal rights for patent applications filed by inventor Waterman Andrew:
Andrew Waterman from Berkeley, US has applied for patents for these inventions. The list has both pending applications and granted patents:
MACRO-OP FUSION FOR PIPELINED ARCHITECTURES
#2 | 2026-03-05TECHNOLOGIES FOR PREDICTION-BASED REGISTER RENAMING
#3 | 2025-12-18FUSION WITH DESTRUCTIVE INSTRUCTIONS
#4 | 2025-10-30LOGGING GUEST PHYSICAL ADDRESS FOR MEMORY ACCESS FAULTS
#5 | 2025-05-29MEMORY PROTECTION FOR GATHER-SCATTER OPERATIONS
#6 | 2024-08-08Macro-Op Fusion for Pipelined Architectures
#7 | 2024-03-28ATOMIC MEMORY OPERATIONS FOR ADDRESS TRANSLATION
#8 | 2024-01-18Fusion with Destructive Instructions
#9 | 2024-01-18Supporting Multiple Vector Lengths with Configurable Vector Register File
#10 | 2024-01-18Memory Request Combination Indication
#11 | 2024-01-11EFFICIENT PROCESSING OF MASKED MEMORY ACCESSES
#12 | 2023-11-16Load-store pipeline selection for vectors
#13 | 2023-11-16Vector Gather with a Narrow Datapath
#14 | 2023-10-05Memory protection for vector operations
#15 | 2023-09-28Memory protection for gather-scatter operations
#16 | 2023-09-28REGISTER RENAMING FOR POWER CONSERVATION
#17 | 2023-06-22Logging Guest Physical Address for Memory Access Faults
#18 | 2023-01-19Processor Power Management Using Instruction Throttling
#19 | 2022-07-28Fetch stage handling of indirect jumps in a processor pipeline
#20 | 2022-03-17Way predictor and enable logic for instruction tightly-coupled memory and instruction cache
#21 | 2021-09-30Fetch stage handling of indirect jumps in a processor pipeline
#22 | 2021-08-19Macro-op fusion
#23 | 2020-07-02Secure predictors for speculative execution
#24 | 2020-07-02Way predictor and enable logic for instruction tightly-coupled memory and instruction cache
#25 | 2020-06-11Macro-op fusion
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