Santa Clara, California
United States
63
2017-09-14
60
2019-03-12
These are the the leading inventors for applications assigned to SOFT MACHINES, INC.:
SOFT MACHINES, INC. based in Santa Clara, US has been assigned the rights to these inventions. The list includes both Pending Applications and Patent Grants:
Single cycle multi-branch prediction including shadow cache for early far branch prediction
#2 | 2016-12-08 ✅ Patent 10,013,254 granted on 2018-07-03Systems and methods for load cancelling in a processor that is connected to an external interconnect fabric
#3 | 2015-10-22 ✅ Patent 9,454,491 granted on 2016-09-27Systems and methods for accessing a unified translation lookaside buffer
#4 | 2015-10-08 ✅ Patent 9,928,179 granted on 2018-03-27Cache replacement policy
#5 | 2015-09-24 ✅ Patent 9,886,416 granted on 2018-02-06Apparatus and method for processing an instruction matrix specifying parallel and dependent operations
#6 | 2015-09-03 ✅ Patent 10,360,031 granted on 2019-07-23Fast unaligned memory access
#7 | 2015-03-05 ✅ Patent 9,361,227 granted on 2016-06-07Systems and methods for faster read after write forwarding using a virtual address
#8 | 2015-02-19 ✅ Patent 9,665,468 granted on 2017-05-30Systems and methods for invasive debug of a processor without processor execution of instructions
#9 | 2015-02-19 ✅ Patent 9,619,382 granted on 2017-04-11Systems and methods for read request bypassing a last level cache that interfaces with an external fabric
#10 | 2015-02-19 ✅ Patent 9,632,947 granted on 2017-04-25Systems and methods for acquiring data for loads at different access times from hierarchical sources using a load queue as a temporary storage buffer and completing the load early
#11 | 2015-02-12METHOD FOR EXECUTING BLOCKS OF INSTRUCTIONS USING A MICROPROCESSOR ARCHITECTURE HAVING A REGISTER VIEW, SOURCE VIEW, INSTRUCTION VIEW, AND A PLURALITY OF REGISTER TEMPLATES
#12 | 2015-02-12METHOD FOR USING REGISTER TEMPLATES TO TRACK INTERDEPENDENCIES AMONG BLOCKS OF INSTRUCTIONS
#13 | 2015-01-22 ✅ Patent 9,627,038 granted on 2017-04-18Multiport memory cell having improved density area
#14 | 2014-12-18 ✅ Patent 9,632,825 granted on 2017-04-25Method and apparatus for efficient scheduling for asymmetrical execution units
#15 | 2014-10-30 ✅ Patent 9,753,691 granted on 2017-09-05Method for a stage optimized high speed adder
#16 | 2014-10-23 ✅ Patent 9,811,342 granted on 2017-11-07Method for performing dual dispatch of blocks and half blocks
#17 | 2014-10-23 ✅ Patent 9,606,935 granted on 2017-03-28Method and apparatus for preventing non-temporal entries from polluting small structures using a transient buffer
#18 | 2014-10-09 ✅ Patent 9,891,915 granted on 2018-02-13Method and apparatus to increase the speed of the load access and data return speed path using early lower address bits
#19 | 2014-09-18 ✅ Patent 9,934,042 granted on 2018-04-03Method for dependency broadcasting through a block organized source view data structure
#20 | 2014-09-18 ✅ Patent 9,811,377 granted on 2017-11-07Method for executing multithreaded instructions grouped into blocks
#21 | 2014-09-18 ✅ Patent 9,582,322 granted on 2017-02-28Method and apparatus to avoid deadlock during instruction scheduling using dynamic port remapping
#22 | 2014-09-18 ✅ Patent 10,140,138 granted on 2018-11-27Methods, systems and apparatus for supporting wide and efficient front-end operation with guest-architecture emulation
#23 | 2014-09-18 ✅ Patent 9,817,666 granted on 2017-11-14Method for a delayed branch implementation by using a front end track table
#24 | 2014-09-18 ✅ Patent 9,823,930 granted on 2017-11-21Method for emulating a guest centralized flag architecture by using a native distributed flag architecture
#25 | 2014-09-18 ✅ Patent 9,575,762 granted on 2017-02-21Method for populating register view data structure by using register template snapshots
#26 | 2014-09-18 ✅ Patent 9,858,080 granted on 2018-01-02Method for implementing a reduced size register view data structure in a microprocessor
#27 | 2014-09-18 ✅ Patent 9,569,216 granted on 2017-02-14Method for populating a source view data structure by using register template snapshots
#28 | 2014-09-18 ✅ Patent 9,436,476 granted on 2016-09-06Method and apparatus for sorting elements in hardware structures
#29 | 2014-09-18 ✅ Patent 9,891,924 granted on 2018-02-13Method for implementing a reduced size register view data structure in a microprocessor
#30 | 2014-09-18 ✅ Patent 9,886,279 granted on 2018-02-06Method for populating and instruction view data structure by using register template snapshots
#31 | 2014-09-18 ✅ Patent 10,275,255 granted on 2019-04-30Method for dependency broadcasting through a source organized source view data structure
#32 | 2014-09-18 ✅ Patent 10,514,926 granted on 2019-12-24Method and apparatus to allow early dependency resolution and data forwarding in a microprocessor
#33 | 2014-09-18 ✅ Patent 10,467,010 granted on 2019-11-05Method and apparatus for nearest potential store tagging
#34 | 2014-09-18 ✅ Patent 10,198,265 granted on 2019-02-05Microprocessor for gating a load operation based on entries of a prediction table
#35 | 2014-09-18 ✅ Patent 10,228,950 granted on 2019-03-12Method and apparatus for guest return address stack emulation supporting speculation
#36 | 2014-09-18 ✅ Patent 10,152,327 granted on 2018-12-11Apparatus for gating a load operation based on entries of a prediction table
#37 | 2014-09-18 ✅ Patent 9,904,625 granted on 2018-02-27Methods, systems and apparatus for predicting the way of a set associative cache
#38 | 2014-09-18Method and Apparatus to Speed up the Load Access and Data Return Speed Path Using Early Lower Address Bits
#39 | 2014-09-18 ✅ Patent 9,740,499 granted on 2017-08-22Method for implementing a line speed interconnect structure
#40 | 2014-06-26 ✅ Patent 9,501,280 granted on 2016-11-22Cache storing data fetched by address calculating load instruction with label used as associated name for consuming instruction to refer
#41 | 2014-06-05 ✅ Patent 9,916,253 granted on 2018-03-13Method and apparatus for supporting a plurality of load accesses of a cache in a single cycle to maintain throughput
#42 | 2014-04-17 ✅ Patent 9,348,754 granted on 2016-05-24Systems and methods for implementing weak stream software data and instruction prefetching using a hardware data prefetcher
#43 | 2014-04-17 ✅ Patent 9,678,882 granted on 2017-06-13Systems and methods for non-blocking implementation of cache flush instructions
#44 | 2014-04-17 ✅ Patent 9,424,046 granted on 2016-08-23Systems and methods for load canceling in a processor that is connected to an external interconnect fabric
#45 | 2014-03-13 ✅ Patent 9,733,944 granted on 2017-08-15Instruction sequence buffer to store branches having reliably predictable instruction sequences
#46 | 2014-01-30 ✅ Patent 9,740,612 granted on 2017-08-22Systems and methods for maintaining the coherency of a store coalescing cache and a load cache
#47 | 2014-01-30 ✅ Patent 9,229,873 granted on 2016-01-05Systems and methods for supporting a plurality of load and store accesses of a cache
#48 | 2014-01-30 ✅ Patent 9,430,410 granted on 2016-08-30Systems and methods for supporting a plurality of load accesses of a cache in a single cycle
#49 | 2014-01-30 ✅ Patent 9,710,399 granted on 2017-07-18Systems and methods for flushing a cache with modified data
#50 | 2013-11-21 ✅ Patent 9,678,755 granted on 2017-06-13Instruction sequence buffer to enhance branch prediction efficiency
#51 | 2013-09-12 ✅ Patent 8,930,674 granted on 2015-01-06Systems and methods for accessing a unified translation lookaside buffer
#52 | 2013-04-11 ✅ Patent 9,053,292 granted on 2015-06-09Processor executing super instruction matrix with register file configurable for single or multiple threads operations
#53 | 2013-01-24 ✅ Patent 9,733,942 granted on 2017-08-15Mapping of guest instruction block assembled according to branch prediction to translated native conversion block
#54 | 2013-01-24 ✅ Patent 9,207,960 granted on 2015-12-08Multilevel conversion table cache for translating guest instructions to native instructions
#55 | 2012-11-22 ✅ Patent 9,442,772 granted on 2016-09-13Global and local interconnect structure comprising routing matrix to support the execution of instruction sequences by a plurality of engines
#56 | 2012-11-22 ✅ Patent 9,940,134 granted on 2018-04-10Decentralized allocation of resources and interconnect structures to support the execution of instruction sequences by a plurality of engines
#57 | 2012-09-27 ✅ Patent 9,766,893 granted on 2017-09-19Executing instruction sequence code blocks by using virtual cores instantiated by partitionable engines
#58 | 2012-09-27 ✅ Patent 9,842,005 granted on 2017-12-12Register file segments for supporting code block execution by using virtual cores instantiated by partitionable engines
#59 | 2012-09-27 ✅ Patent 9,274,793 granted on 2016-03-01Memory fragments for supporting code block execution by using virtual cores instantiated by partitionable engines
#60 | 2012-08-02 ✅ Patent 9,542,187 granted on 2017-01-10Guest instruction block with near branching and far branching sequence construction to native instruction block
#61 | 2012-08-02 ✅ Patent 9,710,387 granted on 2017-07-18Guest instruction to native instruction range based mapping using a conversion look aside buffer of a processor
#62 | 2012-08-02 ✅ Patent 9,639,364 granted on 2017-05-02Guest to native block address mappings and management of native code storage
#63 | 2010-06-24 ✅ Patent 8,677,105 granted on 2014-03-18Parallel processing of a sequential program using hardware generated threads and their instruction groups executing on plural execution units and accessing register file segments using dependency inheritance vectors across multiple engines
Also check out Soft Machines, Inc.'s (Santa Clara, United States) applicant profile with 9 patent applications submitted.
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