San Jose, California
United States
82
2017-09-14
The entities that hold a legal rights for patent applications filed by inventor Abdallah Mohammad:
Mohammad Abdallah from San Jose, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Single cycle multi-branch prediction including shadow cache for early far branch prediction
#2 | 2017-06-08Multilevel conversion table cache for translating guest instructions to native instructions
#3 | 2017-05-04METHOD FOR EMULATING A GUEST CENTRALIZED FLAG ARCHITECTURE BY USING A NATIVE DISTRIBUTED FLAG ARCHITECTURE
#4 | 2017-05-04Method for dependency broadcasting through a source organized source view data structure
#5 | 2017-05-04Method for populating register view data structure by using register template snapshots
#6 | 2017-05-04Method for populating a source view data structure by using register template snapshots
#7 | 2017-04-27UNIFIED SHADOW REGISTER FILE AND PIPELINE ARCHITECTURE SUPPORTING SPECULATIVE ARCHITECTURAL STATES
#8 | 2017-03-09Instruction sequence buffer to enhance branch prediction efficiency
#9 | 2017-03-09Guest instruction to native instruction range based mapping using a conversion look aside buffer of a processor
#10 | 2017-03-09Hardware accelerated conversion system using pattern matching
#11 | 2017-03-09ALLOCATION OF AN INTERCONNECT STRUCTURE COMPRISING SHARED BUSES TO SUPPORT THE EXECUTION OF INSTRUCTION SEQUENCES BY A PLURALITY OF ENGINES
#12 | 2017-03-09Allocation of a segmented interconnect to support the execution of instruction sequences by a plurality of engines
#13 | 2017-01-26Microprocessor accelerated code optimizer
#14 | 2017-01-26HARDWARE ACCELERATION COMPONENTS FOR TRANSLATING GUEST INSTRUCTIONS TO NATIVE INSTRUCTIONS
#15 | 2017-01-12Systems and methods for accessing a unified translation lookaside buffer
#16 | 2016-12-22Methods, systems and apparatus for predicting the way of a set associative cache
#17 | 2016-12-08Systems and methods for load cancelling in a processor that is connected to an external interconnect fabric
#18 | 2016-11-03Guest to native block address mappings and management of native code storage
#19 | 2016-09-29Guest instruction block with near branching and far branching sequence construction to native instruction block
#20 | 2016-08-25Systems and methods for implementing weak stream software data and instruction prefetching using a hardware data prefetcher
#21 | 2016-08-04Variable caching structure for managing physical storage
#22 | 2016-07-21Register file segments for supporting code block execution by using virtual cores instantiated by partitionable engines
#23 | 2016-07-21Executing instruction sequence code blocks by using virtual cores instantiated by partitionable engines
#24 | 2016-06-02Memory fragments for supporting code block execution by using virtual cores instantiated by partitionable engines
#25 | 2016-05-19Systems and methods for non-blocking implementation of cache flush instructions
#26 | 2016-02-11SYSTEMS AND METHODS FOR SUPPORTING A PLURALITY OF LOAD ACCESSES OF A CACHE IN A SINGLE CYCLE
#27 | 2016-02-11Systems and methods for supporting a plurality of load and store accesses of a cache
#28 | 2016-02-11Systems and methods for maintaining the coherency of a store coalescing cache and a load cache
#29 | 2016-01-28USING A CONVERSION LOOK ASIDE BUFFER TO IMPLEMENT AN INSTRUCTION SET AGNOSTIC RUNTIME ARCHITECTURE
#30 | 2016-01-28AN ALLOCATION AND ISSUE STAGE FOR REORDERING A MICROINSTRUCTION SEQUENCE INTO AN OPTIMIZED MICROINSTRUCTION SEQUENCE TO IMPLEMENT AN INSTRUCTION SET AGNOSTIC RUNTIME ARCHITECTURE
#31 | 2016-01-28SYSTEM CONVERTER THAT EXECUTES A JUST IN TIME OPTIMIZER FOR EXECUTING CODE FROM A GUEST IMAGE
#32 | 2016-01-28System for an instruction set agnostic runtime architecture
#33 | 2016-01-28Using a plurality of conversion tables to implement an instruction set agnostic runtime architecture
#34 | 2016-01-28System converter that implements a run ahead run time guest instruction conversion/decoding process and a prefetching process where guest code is pre-fetched from the target of guest branches in an instruction sequence
#35 | 2016-01-28System converter that implements a reordering process through JIT (just in time) optimization that ensures loads do not dispatch ahead of other loads that are to the same address
#36 | 2015-11-12Method and apparatus for providing hardware support for self-modifying code
#37 | 2015-10-22Systems and methods for accessing a unified translation lookaside buffer
#38 | 2015-10-08Cache replacement policy
#39 | 2015-09-03Fast unaligned memory access
#40 | 2015-07-23LOAD STORE BUFFER AGNOSTIC TO THREADS IMPLEMENTING FORWARDING FROM DIFFERENT THREADS BASED ON STORE SENIORITY
#41 | 2015-07-02Accelerated code optimizer for a multiengine microprocessor
#42 | 2015-05-14Virtual load store queue having a dynamic dispatch window with a distributed structure
#43 | 2015-04-09SEMAPHORE METHOD AND SYSTEM WITH OUT OF ORDER LOADS IN A MEMORY CONSISTENCY MODEL THAT CONSTITUTES LOADS READING FROM MEMORY IN ORDER
#44 | 2015-04-02METHOD AND SYSTEM FOR FILTERING THE STORES TO PREVENT ALL STORES FROM HAVING TO SNOOP CHECK AGAINST ALL WORDS OF A CACHE
#45 | 2015-04-02LOCK-BASED AND SYNCH-BASED METHOD FOR OUT OF ORDER LOADS IN A MEMORY CONSISTENCY MODEL USING SHARED MEMORY RESOURCES
#46 | 2015-02-05MICROPROCESSOR ACCELERATED CODE OPTIMIZER
#47 | 2014-11-20MICROPROCESSOR ACCELERATED CODE OPTIMIZER AND DEPENDENCY REORDERING METHOD
#48 | 2014-10-30Method for a stage optimized high speed adder
#49 | 2014-10-23Method for performing dual dispatch of blocks and half blocks
#50 | 2014-09-18Method for dependency broadcasting through a block organized source view data structure
#51 | 2014-09-18Method for executing multithreaded instructions grouped into blocks
#52 | 2014-09-18Methods, systems and apparatus for supporting wide and efficient front-end operation with guest-architecture emulation
#53 | 2014-09-18Method for a delayed branch implementation by using a front end track table
#54 | 2014-09-18Method for emulating a guest centralized flag architecture by using a native distributed flag architecture
#55 | 2014-09-18Method for populating register view data structure by using register template snapshots
#56 | 2014-09-18Method for implementing a reduced size register view data structure in a microprocessor
#57 | 2014-09-18Method for populating a source view data structure by using register template snapshots
#58 | 2014-09-18Method for populating and instruction view data structure by using register template snapshots
#59 | 2014-09-18Method for dependency broadcasting through a source organized source view data structure
#60 | 2014-09-18Methods, systems and apparatus for predicting the way of a set associative cache
#61 | 2014-09-18Method for implementing a line speed interconnect structure
#62 | 2014-04-17Systems and methods for implementing weak stream software data and instruction prefetching using a hardware data prefetcher
#63 | 2014-04-17Systems and methods for non-blocking implementation of cache flush instructions
#64 | 2014-04-17Systems and methods for load canceling in a processor that is connected to an external interconnect fabric
#65 | 2014-03-13Instruction sequence buffer to store branches having reliably predictable instruction sequences
#66 | 2014-01-30Systems and methods for maintaining the coherency of a store coalescing cache and a load cache
#67 | 2014-01-30Systems and methods for supporting a plurality of load and store accesses of a cache
#68 | 2014-01-30Systems and methods for supporting a plurality of load accesses of a cache in a single cycle
#69 | 2014-01-30Systems and methods for flushing a cache with modified data
#70 | 2013-11-21Instruction sequence buffer to enhance branch prediction efficiency
#71 | 2013-09-12Systems and methods for accessing a unified translation lookaside buffer
#72 | 2013-01-24Mapping of guest instruction block assembled according to branch prediction to translated native conversion block
#73 | 2013-01-24Multilevel conversion table cache for translating guest instructions to native instructions
#74 | 2012-11-22Global and local interconnect structure comprising routing matrix to support the execution of instruction sequences by a plurality of engines
#75 | 2012-11-22Decentralized allocation of resources and interconnect structures to support the execution of instruction sequences by a plurality of engines
#76 | 2012-09-27Executing instruction sequence code blocks by using virtual cores instantiated by partitionable engines
#77 | 2012-09-27Register file segments for supporting code block execution by using virtual cores instantiated by partitionable engines
#78 | 2012-09-27Memory fragments for supporting code block execution by using virtual cores instantiated by partitionable engines
#79 | 2012-08-02Guest instruction block with near branching and far branching sequence construction to native instruction block
#80 | 2012-08-02Variable caching structure for managing physical storage
#81 | 2012-08-02Guest instruction to native instruction range based mapping using a conversion look aside buffer of a processor
#82 | 2012-08-02Guest to native block address mappings and management of native code storage
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