Mountain View, California
United States
27
2016-10-04
27
2016-10-04
These are the the leading inventors for applications assigned to Jasper Design Automation, Inc.:
Jasper Design Automation, Inc. based in Mountain View, US has been assigned the rights to these inventions. The list includes both Pending Applications and Patent Grants:
Functional property ranking
#2 | 2016-09-29 ✅ Patent 10,078,714 granted on 2018-09-18Data propagation analysis for debugging a circuit design
#3 | 2016-09-20 ✅ Patent 9,449,196 granted on 2016-09-20Security data path verification
#4 | 2015-08-11 ✅ Patent 9,104,824 granted on 2015-08-11Power aware retention flop list analysis and modification
#5 | 2015-04-09 ✅ Patent 8,990,745 granted on 2015-03-24Manipulation of traces for debugging behaviors of a circuit design
#6 | 2015-04-09 ✅ Patent 9,081,927 granted on 2015-07-14Manipulation of traces for debugging a circuit design
#7 | 2015-04-02 ✅ Patent 8,984,461 granted on 2015-03-17Visualization constraints for circuit designs
#8 | 2015-02-10 ✅ Patent 8,954,904 granted on 2015-02-10Veryifing low power functionality through RTL transformation
#9 | 2014-10-14 ✅ Patent 8,863,049 granted on 2014-10-14Constraining traces in formal verification
#10 | 2014-09-09 ✅ Patent 8,831,925 granted on 2014-09-09Indexing behaviors and recipes of a circuit design
#11 | 2014-09-02 ✅ Patent 8,826,201 granted on 2014-09-02Formal verification coverage metrics for circuit design properties
#12 | 2014-05-27 ✅ Patent 8,739,092 granted on 2014-05-27Functional property ranking
#13 | 2014-05-20 ✅ Patent 8,731,894 granted on 2014-05-20Indexing behaviors and recipes of a circuit design
#14 | 2013-10-29 ✅ Patent 8,572,527 granted on 2013-10-29Generating properties for circuit designs
#15 | 2013-09-03 ✅ Patent 8,527,911 granted on 2013-09-03Comprehending a circuit design
#16 | 2013-08-20 ✅ Patent 8,516,421 granted on 2013-08-20Generating circuit design properties from signal traces
#17 | 2012-07-17 ✅ Patent 8,225,249 granted on 2012-07-17Static formal verification of a circuit design using properties defined with local variables
#18 | 2012-06-19 ✅ Patent 8,205,187 granted on 2012-06-19Generalizing and inferring behaviors of a circuit design
#19 | 2012-01-24 ✅ Patent 8,103,999 granted on 2012-01-24Debugging of counterexamples in formal verification
#20 | 2011-02-22 ✅ Patent 7,895,552 granted on 2011-02-22Extracting, visualizing, and acting on inconsistencies between a circuit design and its abstraction
#21 | 2010-01-12 ✅ Patent 7,647,572 granted on 2010-01-12Managing formal verification complexity of designs with multiple related counters
#22 | 2009-03-17 ✅ Patent 7,506,288 granted on 2009-03-17Interactive analysis and debugging of a circuit design during functional verification of the circuit design
#23 | 2008-09-02 ✅ Patent 7,421,668 granted on 2008-09-02Meaningful visualization of properties independent of a circuit design
#24 | 2008-08-26 ✅ Patent 7,418,678 granted on 2008-08-26Managing formal verification complexity of designs with counters
#25 | 2007-06-26 ✅ Patent 7,237,208 granted on 2007-06-26Managing formal verification complexity of designs with datapaths
#26 | 2006-06-20 ✅ Patent 7,065,726 granted on 2006-06-20System and method for guiding and optimizing formal verification for a circuit design
#27 | 2006-03-28 ✅ Patent 7,020,856 granted on 2006-03-28Method for verifying properties of a circuit model
Also check out Jasper Design Automation, Inc.'s (Mountain View, United States) applicant profile with 9 patent applications submitted.
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