Inventor profile of:

Lawrence Loh

City:

Milpitas, California

Country:

United States

Published Applications:

16

Last publication date:

2019-02-12

Top Assignees for applications by Lawrence Loh

The entities that hold a legal rights for patent applications filed by inventor Loh Lawrence:

Recent patent applications by Loh Lawrence

Lawrence Loh from Milpitas, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2019-02-12
US15199059
Physics

Methods, systems, and articles of manufacture for verifying an electronic design using hierarchical clock domain crossing verification techniques

#2 | 2018-04-03
US15269931
Physics

Security data path verification

#3 | 2018-03-20
US15269919
Physics

Security data path verification

#4 | 2017-04-25
US14675699
Physics

Methods, systems, and computer program product for verifying electronic designs with clock domain crossing paths

#5 | 2016-09-20
US13867341
Physics

Security data path verification

#6 | 2015-08-11
US13874398
Physics

Power aware retention flop list analysis and modification

#7 | 2015-02-10
US13874388
Physics

Veryifing low power functionality through RTL transformation

#8 | 2014-10-14
US12961389
-

Constraining traces in formal verification

#9 | 2014-09-09
US12797467
-

Indexing behaviors and recipes of a circuit design

#10 | 2014-05-20
US13618632
-

Indexing behaviors and recipes of a circuit design

#11 | 2013-02-19
US13404403
-

Formal verification of deadlock property

#12 | 2010-01-12
US11851330
-

Managing formal verification complexity of designs with multiple related counters

#13 | 2008-10-14
US11063399
-

System and method for determining and identifying signals that are relevantly determined by a selected signal in a circuit design

#14 | 2008-08-26
US10909099
-

Managing formal verification complexity of designs with counters

#15 | 2007-06-26
US10818711
-

Managing formal verification complexity of designs with datapaths

#16 | 2007-01-02
US10745993
-

System and method for identifying design efficiency and effectiveness parameters for verifying properties of a circuit model

InventorID:

7158604 ⎘