171752 ⎘
Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere; Testing of electronic circuits, e.g. by signal tracer; Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]; Specific types of tests or tests for a specific type of fault, e.g. thermal mapping, shorts testing Functional tests, e.g. boundary scans, using the normal I/O contacts
METHOD AND APPARATUS FOR CIRCUIT BOARD DETECTION, COMPUTER DEVICE, STORAGE MEDIUM, AND PROGRAM PRODUCTS
#2WIRING BOARD AND MOUNTING STRUCTURE
#3Methods for Verifying Integrity and Authenticity of a Printed Circuit Board
#4STRUCTURE AND METHOD FOR FAILURE DIAGNOSIS OF PCB BOARD FOR ARTICLE TRANSPORT ELEVATOR
#5INTERFACE TO FULL AND REDUCED PIN JTAG DEVICES
#6UNIVERSAL SOCKET TEST CARD
#7CIRCUIT BOARD AND MONITORING METHOD THEREFOR
#8SEMICONDUCTOR TEST DEVICE AND SYSTEM AND TEST METHOD USING THE SAME
#9Terahertz Plasmonics for Testing Very Large-Scale Integrated Circuits under Bias
#10Interface to full and reduced pin JTAG devices
#11Differential aging monitor circuits and techniques for assessing aging effects in semiconductor circuits
#12Circuits and techniques for assessing aging effects in semiconductor circuits
#13Systems and methods for circuit failure protection
#14Memory device architecture coupled to a system-on-chip
#15Reconfigurable JTAG architecture for implementation of programmable hardware security features in digital designs
#16Circuit board and method and device related to the same
#17Method and/or system for testing devices in non-secured environment
#18Flexible test systems and methods
#19Terahertz plasmonics for testing very large-scale integrated circuits under bias
#20Systems, methods and devices for high-speed input/output margin testing
#21Design System For Test Adaptor Card And Method Thereof
#22Memory device architecture coupled to a System-on-Chip
#23Interface to full and reduced pin JTAG devices
#24Semiconductor test device and system and test method using the same
#25Inspection Method for Pins and Vias of Differential Signal Lines
#26Method of and an arrangement for analyzing manufacturing defects of multi-chip modules made without known good die
#27ONLINE TEST DATA RECORD AND OFFLINE DATA CONVERSION ANALYSIS SYSTEM, AND METHOD
#28Test access port circuit capable of increasing transmission throughput
#29Distributed control modules with built-in tests and control-preserving fault responses
#30Electrically testing cleanliness of a panel having an electronic assembly
#31Apparatus and method and computer program product for verifying memory interface
#32SMART DECISION FEEDBACK DEVICE AND METHOD FOR INSPECTING CIRCUIT BOARD
#33Switching FPI between FPI and RPI from received bit sequence
#34System and device for automatic signal measurement
#35Device and method for testing motherboard
#36Systems and methods for determining whether a circuit is operating properly
#37Counterfeit integrated circuit detection by comparing integrated circuit signature to reference signature
#38Apparatus and method for performing a scalability check on a hardware description language representation of a circuit
#39Shadow protocol circuit producing enable, address, and address control signals
#40Terahertz plasmonics for testing very large-scale integrated circuits under bias
#41Testing circuit board with self-detection function and self-detection method thereof
#42Apparatus, method, and system for testing IC chip
#43Independently driving built-in self test circuitry over a range of operating conditions
#44Dual gate array substrate, testing method, display panel and display apparatus
#45System and computer program product for performing comprehensive functional and diagnostic circuit card assembly (CCA) testing
#46Apparatus, method, and system for testing IC chip
#47Repairing system and repairing method for a CABC module
#48Shadow protocol detection, address circuits with command shift, update registers
#49Systems and methods for determining whether a circuit is operating properly
#50Tap SPC with tap state machine reset and clock control
#51Full/reduced pin JTAG interface shadow protocol detection, command, address circuits
#52Serial/parallel control, separate tap, master reset synchronizer for tap domains
#53Substrate with state machine circuitry and tap state monitor circuitry
#54Monitoring on-chip clock control during integrated circuit testing
#55Scan cell selection for partial scan designs
#56Test board and method for qualifying a printed circuit board assembly and/or repair process
#57Circuit board testing system
#58Operating state machine from reset to poll in to reset
#59Identifying a signal on a printed circuit board under test
#60Interface circuitry with JTAG interface, full and reduced pin interfaces
#61SYSTEM AND METHOD FOR ELECTROSTATIC DISCHARGE TESTING
#62Asynchronous programmable JTAG-based interface to debug any system-on-chip states, power modes, resets, clocks, and complex digital logic
#63Method and apparatus for testing I/O boundary scan chain for SoC's having I/O's powered off by default
#64Transitioning POLL IN to set MRST and CE high states
#65Master reset and synchronizer circuit with data and clock inputs
#66JTAG shadow protocol circuit with detection, command and address circuits
#67Method and system for testing an electric circuit
#68Test device and test method for multimedia data card and mobile-phone multimedia data card
#69Identifying a signal on a printed circuit board under test
#70Clock controller for JTAG interface
#71Terminal discriminating apparatus and terminal discriminating method using the same
#72Method and apparatus for testing electrical connections on a printed circuit board
#73Shadow protocol circuit having full and reduced pin select outputs
#74Testing device for printed circuit boards
#75Electronic device and method for testing a circuit board
#76Electronic device and method for testing a circuit board
#77Electronic device and method for testing a circuit board
#78Tap and control with data I/O, TMS, TDI, and TDO
#79Optimized JTAG interface
#80Interface to full and reduced pin JTAG devices
#81TESTING APPARATUS AND TESTING METHOD
#82Optimized JTAG interface
#83Connector, printed circuit board, connecting device connecting them, and method of testing electronic part, using them
#84Circuit card assembly testing system for a missile and launcher test set
#85Test circuit capable of sequentially performing boundary scan test and test method thereof
#86Method of manufacturing a system in package
#87Microcomputer and method of testing the same
#88Method and apparatus for repeatable drive strength assessments of high speed memory DIMMs
#89Connector, printed circuit board, connecting device connecting them, and method of testing electronic part, using them
#90Optimized JTAG interface
#91Boundary scan connector test method capable of fully utilizing test I/O modules
#92Interface to full and reduce pin JTAG devices
#93STACKED PACKAGE SCREENING
#94Analog boundary scanning based on stray capacitance
#95Micro telecommunications computing architecture, MicroTCA, test system and method
#96System and method for conducting BIST operations
#97Connector, printed circuit board, connecting device connecting them, and method of testing electronic part, using them
#98Method and apparatus for testing an ultrasound system
#99Test buffer design and interface mechanism for differential receiver AC/DC boundary scan test
#100Controller receiving combined TMS/TDI and suppyling separate TMS and TDI
#101Boundary scan testing system
#102Multiple device scan chain emulation/debugging
#103Wireless hardware debugging
#104Device and method for JTAG test
#105JTAG interface using existing I/O bus
#106Method and apparatus for testing an electronic device
#107Method and apparatus for testing a transmission path
#108System and method for conducting BIST operations
#109Store scan data in trace arrays for on-board software access
#110Connector circuit board
#111Semiconductor chip
#112Trace information queueing system
#113Apparatus and method for testing motherboard having PCI express devices
#114Testing device for printed circuit boards
#115Method and apparatus for circuit board inspection capable of monitoring inspection signals by using a signal monitor incorporated in the apparatus
#116Programmable hysteresis for boundary-scan testing
#117Directional control of scan capture through shared wrapper cells
#118Power-collapsible boundary scan
#119Limited pin test interface with analog test bus
#120Apparatus, method, and system for testing IC chip
#121Method and apparatus for efficient hierarchical chip testing and diagnostics with support for partially bad dies
#122Performance screen ring oscillator formed from multi-dimensional pairings of scan chains