171827 ⎘
Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere; Testing of electronic circuits, e.g. by signal tracer; Testing of digital circuits Debugging aspects, e.g. using test circuits for debugging, using dedicated debugging test circuits
SYSTEM AND METHOD FOR DEBUGGING CLB LOGIC ELEMENT STATES USING ONLY ONE PIN
#2DEBUG SYSTEM AND METHOD FOR OPERATING A DEBUG SYSTEM
#3REAL-TIME DEBUG IN LOW-POWER DEVICES
#4AUTOMATICALLY MAPPING EVENT-BASED SIMULATION DATA TO CYCLE-BASED SIMULATION IN HYBRID HARDWARE DEBUG PLATFORMS
#53D INTEGRATED CIRCUIT WITH ENHANCED DEBUGGING CAPABILITY
#6DEBUG INFRASTRUCTURE FOR MEMORY SYSTEMS
#7CO-DEBUG OF PROCESSING CONDITIONS OF LOGIC DEVICES
#8CONFIGURABLE MULTILAYERED OVERRIDE SYSTEM AND METHOD FOR CIRCUMVENTING SEMICONDUCTOR CIRCUITRY WITH UNPREDICTABLE SILICON BEHAVIOR
#9DEBUG TRACE MICROSECTORS
#10TEST (DFT) AND DESIGN FOR DEBUG (DFD) GATED POWER DOMAINS
#11DEVICE UNDER TEST, FAULT INJECTION TESTING SYSTEM AND METHOD FOR FAULT INJECTION TESTING USING AN ON-CHIP FAULT TESTING MODULE
#12Debug Trace Fabric for Integrated Circuit
#13Processor debugging over an interconnect fabric
#14Error protection analysis of an integrated circuit
#15STORAGE SYSTEM AND AN OPERATING METHOD THEREOF
#16METHODS AND SYSTEMS FOR REMOTE ACCESS HARDWARE TESTING
#17INFIELD TEST AND DEBUG
#18TECHNOLOGIES FOR A UNIFIED TEST AND DEBUG ARCHITECTURE
#19Test system that converts command syntaxes
#20TECHNIQUES FOR DEBUG, SURVIVABILITY, AND INFIELD TESTING OF A SYSTEM-ON-A-CHIP OR A SYSTEM-ON-A-PACKAGE
#21Semiconductor device, debug system, and debug method
#22MEMORY, MEMORY SYSTEM AND METHOD OF CONTROLLING STORAGE DEVICE
#23Methods and systems for remote access hardware testing
#243D INTEGRATED CIRCUIT WITH ENHANCED DEBUGGING CAPABILITY
#25PROVIDING CONFIGURABLE SECURITY FOR INTELLECTUAL PROPERTY CIRCUITS OF A PROCESSOR
#26INFORMATION PROCESSING APPARATUS AND INFORMATION PROCESSING METHOD
#27Apparatus and method for electrically coupling a unit under test with a debugging component
#28ERROR DIAGNOSIS CIRCUIT AND METHOD FOR OPERATING A DEVICE
#29TEST AND DEBUG SUPPORT WITH HBI CHIPLET ARCHITECTURE
#30Methods and systems for identifying flaws and bugs in integrated circuits, for example, microprocessors
#31Reduced signaling interface method and apparatus
#32Multi-die debug stop clock trigger
#33DEBUG SYSTEM AND DEBUG METHOD
#34Voltage monitoring circuit for interface
#35Scan apparatus capable of fault diagnosis and scan chain fault diagnosis method
#36Debug trace fabric for integrated circuit
#37Method for real-time firmware configuration and debugging apparatus
#38SECURED DEBUG
#39COMMUNICATION METHOD AND ITS SYSTEM BETWEEN INTERCONNECTED DIE AND DSP/FPGA
#40Interface system for interconnected die and MPU and communication method thereof
#41Debug trace microsectors
#42Method and apparatus for debugging integrated circuit systems using scan chain
#43Debug system providing debug protection
#44Extended JTAG controller and method for functional debugging using the extended JTAG controller
#45INPUT-OUTPUT DEVICE WITH DEBUG CONTROLLER
#46Device, system and method to support communication of test, debug or trace information with an external input/output interface
#47Debug support device, debug support method, and computer readable storage medium
#48Authenticated debug for computing systems
#49Debug probe for measuring at least one property of a target system
#50Techniques to enable integrated circuit debug across low power states
#51DEBUG DATA COMMUNICATION SYSTEM FOR MULTIPLE CHIPS
#52Systems and methods for intellectual property-secured, remote debugging
#53Integrated circuit with reduced signaling interface
#54Embedded logic analyzer and integrated circuit including the same
#55Secure debug architecture
#56JTAG bus communication method and apparatus
#57SYSTEM AND METHOD FOR IDENTIFYING DESIGN FAULTS OR SEMICONDUCTOR MODELING ERRORS BY ANALYZING FAILED TRANSIENT SIMULATION OF AN INTEGRATED CIRCUIT
#58Method for identifying and compensating for systems errors
#59Test method and test system
#60Joint test action group transmission system capable of transmitting data continuously
#61Debugging solution for multi-core processors
#62Method of and an arrangement for analyzing manufacturing defects of multi-chip modules made without known good die
#63Reduced signaling interface circuit
#64Interfaces for wireless debugging
#65Device such as a connected object provided with means for checking the execution of a program executed by the device
#66Method for analyzing a simulation of the execution of a quantum circuit
#67Debug interface recorder and replay unit
#68Core-Only System Management Interrupt
#69Systems and methods for intellectual property-secured, remote debugging
#70Device, system and method to support communication of test, debug or trace information with an external input/output interface
#71Time-limited debug mode
#72Method for managing a return of a product for analysis and corresponding product
#73Debug tool for test instruments coupled to a device under test
#74Integrated circuit and application processor
#75Apparatus and method using debug status storage element
#76DEVICE SUCH AS A CONNECTED OBJECT PROVIDED WITH MEANS FOR CHECKING THE EXECUTION OF A PROGRAM EXECUTED BY THE DEVICE
#77Debug command execution using existing datapath circuitry
#78Secure coprocessor assisted hardware debugging
#79Precise verification of a logic problem on a simulation accelerator
#80Serial data communication modes on TDI/TDO, receive TMS, send TMS
#81Combinatorial serial and parallel test access port selection in a JTAG interface
#82Server and debugging method therefor
#83Apparatuses and methods for a multiple master capable debug interface
#84Secure debug system for electronic devices
#85Reconfiguring monitoring circuitry
#86Smart and efficient protocol logic analyzer configured within automated test equipment (ATE) hardware
#87Sequential test access port selection in a JTAG interface
#88Debug controller circuit
#89Real-time oscilloscope with a built-in time domain reflectometry (TDR) and/or time-domain transmission (TDT) function
#90System on chip and operating method thereof
#91Extracting debug information from FPGAs in multi-tenant environments
#92NON-INTRUSIVE ON-CHIP DEBUGGER WITH REMOTE PROTOCOL SUPPORT
#93Entering home state after soft reset signal after address match
#94Storage device with debug namespace
#95Methods and apparatus for performing design for debug via protocol interface
#96Device, system and method to support communication of test, debug or trace information with an external input/output interface
#97Tap, counter storing value of serial access by communication circuitry
#98System and method for time stamp synchronization
#99Systems and methods for debugging access
#100Test device for testing integrated circuit
#101Method for managing a return of a product for analysis and corresponding product
#102Programmable radio transceivers
#103Sequential test access port selection in a JTAG interface
#104Combinatorial serial and parallel test access port selection in a JTAG interface
#105Signals on tap bi-directional TMS terminal selecting serial communication register
#106JTAG scans through packetization
#107Core-only system management interrupt
#108Selective event filtering
#109Intelligent function unit and programmable logic controller system
#110Interfaces for wireless debugging
#111Debugging translation block and debugging architecture
#112MICROPROCESSOR INTERFACES
#113Test circuit to debug missed test clock pulses
#114System-on-chip including CPU operating as debug host and method of operating the same
#115Reconfiguring debug circuitry
#116Device, system and method for providing on-chip test/debug functionality
#117Method and diagnostic apparatus for performing diagnostic operations upon a target apparatus using transferred state and emulated operation of a transaction master
#118Scan data control apparatus and electronic system having the same
#119EMBEDDED FIRMWARE CONTENT TRACING
#120Adapter circuitry with link and system interfaces to core circuitry
#121Lightweight, low overhead debug bus
#122Address/instruction registers, target domain interfaces, control information controlling all domains
#123Test mode isolation and power reduction in embedded core-based digital systems of integrated circuits (ICs) with multiple power domains
#124Highly flexible performance counter and system debug module
#125APPARATUS AND METHOD FOR PROVIDING DEBUG INFORMATION VIA POWER RAIL IN POWER STATE WHERE DEBUG INTERFACE IS DISABLED
#126Internal circuit TMS input, FIFO coupled to parallel-input serial-output register
#127TMS pin for mode signal and output for read data
#128Scan path only one-bit scan register when component not selected
#129Integrated circuit and application processor
#130Extracting debug information from FPGAs in multi-tenant environments
#131JTAG DEBUG APPARATUS AND JTAG DEBUG METHOD
#132METHOD FOR ENABLING CPU-JTAG DEBUGGER CONNECTION OR IMPROVING ITS PERFORMANCE FOR MULTI-CLOCK DESIGNS RUNNING ON FPGA OR EMULATION SYSTEMS
#133Soundwire-based embedded debugging in an electronic device
#134Hardware debug host
#135Apparatuses and methods for a multiple master capable debug interface
#136Techniques for secure debugging and monitoring
#137Adaptive debug tracing for microprocessors
#138Signal tracing using on-chip memory for in-system post-fabrication debug
#139Debug architecture
#140Reconfigurable test access port with finite state machine control
#141Debugging method executed via scan chain for scan test and related circuitry system
#142Calibration tool assembly and method of using same
#143Status register between test data I/O of scan port SUT
#144System on chip and secure debugging method
#145Debugging scan latch circuits using flip devices
#146Adapter circuitry with global bypass register, legacy test data, multiplexer
#147Waveform mapping and gated laser voltage imaging
#148System and method for establishing a trusted diagnosis/debugging agent over a closed commodity device
#149Method of debugging PLC by using general-purpose microprocessor
#150Device, system and method to support communication of test, debug or trace information with an external input/output interface
#151Efficiency of cycle-reproducible debug processes in a multi-core environment
#152LBIST debug controller
#153Debugging scan latch circuits using flip devices
#154Debugging system and method
#155Integrated circuit verification using parameterized configuration
#156Addressable tap domain selection circuit with instruction and linking circuits
#157Reconfiguring debug circuitry
#158Debug adapter
#159Embedded logic analyzer and integrated circuit including the same
#160TMS serial communication circuitry coupled to tap IR enable output
#161On-the-fly test and debug logic for ATPG failures of designs using on-chip clocking
#162Flash memory controller, data processing system with flash memory controller and method of operating a flash memory controller
#163Orientation indicator with pin signal alteration
#164Efficiency of cycle-reproducible debug processes in a multi-core environment
#165Delayed authentication debug policy
#166Debug architecture
#167DEBUG TRIGGER INTERFACE FOR NON-DEBUG DOMAIN SYSTEM RESET
#168Debug circuit, semiconductor device, and debug method
#169Efficient event detection
#170Serial wire debug bridge
#171Blocking the effects of scan chain testing upon a change in scan chain topology
#172Debug circuit, semiconductor device, and debug method
#173High-frequency signal observations in electronic systems
#174System debug using an all-in-one connector
#175DEBUGGER AND DEBUGGING SYSTEM
#176Apparatus for detecting bugs in logic-based processing devices
#177Test IP-based A.T.E. instrument architecture
#178Registers for post configuration testing of programmable logic devices
#179Low-overhead debug architecture using a speculative, concurrent and distributed data capture and propagation scheme
#180Reprogramming a port controller via its own external port
#181Blocking the effects of scan chain testing upon a change in scan chain topology
#182Debug circuit for an integrated circuit
#183Cycle deterministic functional testing of a chip with asynchronous clock domains
#184Debug circuit, semiconductor device, and debug method
#185Transporting ordered test data, mode select, ready, precharge packet bits
#186Debugging circuit, debugger device, and debugging method
#187Signal tracing using on-chip memory for in-system post-fabrication debug
#188Functional testing of an integrated circuit chip
#189Techniques for secure debugging and monitoring
#190TAP addressable circuit with bi-directional TMS and second signal lead
#191Blocking the effects of scan chain testing upon a change in scan chain topology
#192Debug architecture
#193Systems and methods for monitoring hardware observation points within a system on a Chip (SoC)
#194Bi-directional TCK lead carrying TCK and frame data in/out signal
#195Monitoring on-chip clock control during integrated circuit testing
#196DEBUGGING SYSTEM AND METHOD
#197System and method for sequential testing across multiple devices
#198Method and apparatus for connecting debug interface to processing circuits without sideband interface
#199Remote station and method for re-enabling a disabled debug capability in a system-on-a-chip device
#200Chip debug during power gating events
#201Routing debug messages
#202Blocking the effects of scan chain testing upon a change in scan chain topology
#203Digital device and method
#204Hardware state data logger for silicon debug
#205Monitoring functional testing of an integrated circuit chip
#206Methods and apparatus for debugging lowest power states in System-On-Chips
#207IC test circuitry and adapter with data transport control register
#208On-the-fly test and debug logic for ATPG failures of designs using on-chip clocking
#209Integrated circuit with a high-speed debug access port
#210Trace-data processing and profiling device
#211Tap, data input, output circuitry coupled to mode select lead
#212Blocking the effects of scan chain testing upon a change in scan chain topology
#213Debug apparatus and methods for dynamically switching power domains
#214Debug apparatus and methods for dynamically switching power domains
#215SYSTEM-ON-CHIP, METHOD OF MANUFACTURE THEREOF AND METHOD OF COMMUNICATING DIAGNOSTIC DATA
#216Integrated circuit (IC) for reconstructing values of flip-flops connected in a scan-chain by using a joint test action group (JTAG) interface, a method of operating the IC, and devices having the IC
#217Method and apparatus for multi-chip reduced pin cross triggering to enhance debug experience
#218I/O circuitry free of test clock coupled with destination/source circuitry
#219System on a chip FPGA spatial debugging using single snapshot
#220DEBUGGING CIRCUIT AND CIRCUIT BOARD USING SAME
#221Debug system, apparatus and method thereof for providing graphical pin interface
#222SCAN TEST CIRCUITRY WITH CONTROL CIRCUITRY CONFIGURED TO SUPPORT A DEBUG MODE OF OPERATION
#223Test access port and TMS communication circuitry with state machines
#224Debugging in a semiconductor device test environment
#225Remote monitoring systems and related methods and recording mediums using the same
#226Blocking the effects of scan chain testing upon a change in scan chain topology
#227Processor switchable between test and debug modes
#228Logic circuit for the gathering of trace data
#229Concurrent host operation and device debug operation with single port extensible host interface (xHCI) host controller
#230CIRCUITS AND METHODS FOR FUNCTIONAL TESTING OF INTEGRATED CIRCUIT CHIPS
#231Hot-plugging debugger architectures
#232System and method for hybrid board-level diagnostics
#233DEBUGGING MULTIPLE EXCLUSIVE SEQUENCES USING DSM CONTEXT SWITCHES
#234On-die logic analyzer for semiconductor die
#235Debug architecture
#236Prioritizing transport of debug data on an integrated circuit chip by data type
#237JTAG-based programming and debug
#238Dynamic device identification for making a JTAG debug connection with a internet browser
#239Debugging system using optical transmission
#240Methods and structure for correlating multiple test outputs of an integrated circuit acquired during separate instances of an event
#241System and method for processing signal
#242On-die logic analyzer for semiconductor die
#243Debug barrier transactions
#244Method and circuitry for debugging a power-gated circuit
#245Tokenized resource access
#246METHOD FOR DOCUMENT PAGE DELIVERY TO A MOBILE COMMUNICATION DEVICE
#247TDI multiplexer gating controlled by override selection logic
#248Bi-directional TMS lead carrying TMS and frame data in/out signals
#249Address and instruction controller with TCK, TMS, address match inputs
#250Circuit for detecting and recording chip fails and the method thereof
#251Debug access with programmable return clock
#252DEBUG STATE MACHINE CROSS TRIGGERING
#253Debug state machine cross triggering
#254Adapter leads connected to test circuitry and third leads set
#255APPARATUS AND METHOD OF AUTHENTICATING JOINT TEST ACTION GROUP (JTAG)
#256On-chip service processor
#257Communication of a diagnostic signal and a functional signal by an integrated circuit
#258Target device providing debugging function and test system comprising the same
#259Inverter and TMS clocked flip-flop pairs between TCK and reset
#260BDX DATA IN STABLE STATES
#261Source and destination data circuitry coupled to bi-directional TMS lead
#262Reduced signaling interface method and apparatus
#263Method for document delivery to a mobile communication device
#264Integrated circuit including a programmable logic analyzer with enhanced analyzing and debugging capabilities and a method therefor
#265On-die logic analyzer for semiconductor die
#266Generic debug external connection (GDXC) for high integration integrated circuits
#267Comparing supplied and sampled link ID bits on TMS lead
#268Effecting adapter commands upon sequential target system TAP states
#269Debugging module for electronic device and method thereof
#270I/O switches and serializer for each parallel scan register
#271BDX data in stable states
#272SYSTEM AND METHOD FOR IMPROVED PERFORMANCE AND OPTIMIZATION OF DATA EXCHANGES OVER A COMMUNICATIONS LINK
#273JTAG bus communication method and apparatus
#274TRACE DEVICE AND TRACE METHOD FOR FAILURE ANALYSIS
#275JTAG debug test system adapter with three sets of leads
#276Failure analysis apparatus, method
#277METHOD FOR DOCUMENT DELIVERY TO A MOBILE COMMUNICATION DEVICE
#278On-chip service processor
#279Apparatus and method of authenticating joint test action group (JTAG)
#280Method and system for debugging using replicated logic and trigger logic
#281Saving debugging contexts with periodic built-in self-test execution
#282Tokenized resource access
#283Reduced signaling interface method and apparatus
#284Diagnostic device, diagnostic method, program, and recording medium
#285System debugging method, system debugging equipment, processor, wireless-communications interface IC and interface method thereof
#286TESTABLE MULTIPROCESSOR SYSTEM AND A METHOD FOR TESTING A PROCESSOR SYSTEM
#287Mode selection based on special sequence of state machine states
#288Secure debug interface and memory of a media security circuit and method
#289METHOD AND SYSTEM FOR VALIDATING A PROCESSOR IN A SEMICONDUCTOR ASSEMBLY
#290Controller applying stimulus data while continuously receiving serial stimulus data
#291System and method for sharing a communications link between multiple communications protocols
#292Emulation export sequence with distrubuted control
#293Performance software instrumentation and analysis for electronic design automation
#294Local and global address compare with tap interface TDI/TDO lead
#295JTAG bus communication method and apparatus
#296Semiconductor integrated circuit and debug mode determination method
#297Semiconductor test program debug device
#298Semiconductor integrated circuit and debugging system
#299Integrated circuit and integrated circuit package
#300Select signal and component override signal controlling multiplexing TDI/TDO