Integrated circuit testing module including signal shaping interface

Circuits, systems and methods for adjusting clock signals based on measured performance characteristics

TEST APPARATUS AND TEST METHOD

TAM with scan frame copy register coupled with serial output

Method And Circuit For Testing And Characterizing High Speed Signals Using An ON-Chip Oscilloscope

On-chip comparison and response collection tools and techniques

Input linking circuitry connected to test mode select and enables

Instruction register delay select outputs to clock delay circuitry

Test access port with address and command capability

Inverter and TMS clocked flip-flop pairs between TCK and reset

Test apparatus and test method

Semiconductor device and diagnostic method thereof

Shadow protocol circuit having full and reduced pin select outputs

Measuring a time period

Generating a time delayed event

Method to detect clock tampering

DOUBLE DATA RATE TEST INTERFACE AND ARCHITECTURE

TEST APPARATUS AND TEST METHOD

Gates and sync circuitry connecting TAP to serial communications circuitry

IC with TAP, DIO interface, SIPE, and PISO circuits

Link instruction register with instruction register, and gate and multiplexer

Tap and control with data I/O, TMS, TDI, and TDO

Reduced signaling interface method and apparatus

Method and apparatus for reconfigurable at-speed test clock generator

IEEE 1149.1 and P1500 test interfaces combined circuits and processes

Source and destination data circuitry coupled to bi-directional TMS lead

Multiplexer selecting STP clock signal with tap control outputs

Reduced signaling interface method and apparatus

Communication between controller and addressed target devices over data signal

Clock signal amplification circuit, control method thereof, and clock signal distribution circuit

Inverted TCK access port selector selecting one of plural TAPs

Acquisition of silicon-on-insulator switching history effects statistics

Interconnections for plural and hierarchical P1500 test wrappers

Optimized JTAG interface

Interface to full and reduced pin JTAG devices

SIGNAL PROCESSING APPARATUS INCLUDING BUILT-IN SELF TEST DEVICE AND METHOD FOR TESTING THEREBY

Serial compressed data I/O in a parallel test compression architecture

CLOCK SIGNAL TEST APPARATUS AND METHOD

Test apparatus

Wafer scale testing using a 2 signal JTAG interface

Reduced signaling interface method and apparatus

DDR gate and delay clock circuitry for parallel interface registers

Selectable JTAG or trace access with data store and output

Wrapper leads gating TAP instruction and data registers

IEEE 1149.1 and P1500 test interfaces combined circuits and processes

Self-test design methodology and technique for root-gated clocking structure

JTAG bus communication method and apparatus

JTAG debug test system adapter with three sets of leads

Timer unit, system, computer program product and method for testing a logic circuit

Dual mode test access port method and apparatus

Clock circuits and counting values in integrated circuits

MEASUREMENT APPARATUS FOR IMPROVING PERFORMANCE OF STANDARD CELL LIBRARY

Serial I/O using JTAG TCK and TMS signals

Signal Integrity Measurement Systems and Methods Using a Predominantly Digital Time-Base Generator

Clock signal generation circuit

Semiconductor device having built-in self-test circuit and method of testing the same

Variable-loop-path ring oscillator test circuit and systems and methods utilizing same

Hardware and method to test phase linearity of phase synthesizer

Clock delay circuits and multiplexer connected to boundary scan circuitry

Semiconductor integrated circuit and method for testing semiconductor integrated circuit

Optimized JTAG interface

TAM with scan frame copy register coupled with serial output

Clock data recovery circuit and method

Reduced signaling interface method and apparatus

Demodulation apparatus, test apparatus and electronic device

For testability technique for phase detectors used in digital feedback delay locked loops

Automatic scan format selection based on scan topology selection

Selecting a scan topology

IEEE 1149.1 and P1500 test interfaces combined circuits and processes

Series equivalent scans across multiple scan topologies

Ascertaining configuration by storing data signals in a topology register

Dynamic broadcast of configuration loads supporting multiple transfer formats

Alternate Signaling Mechanism Using Clock and Data

System and method for on-chip duty cycle measurement

Multi-clock system-on-chip with universal clock control modules for transition fault test at speed multi-core

TAP domain selection circuit with selected TDI/TDO or TDO lead

Parallel scan paths with header data circuitry and header return circuitry

Compare circuit receiving scan register and inverted clock flip-flop data

Selectable JTAG or trace access with data store and output

Systemic Frequency Adjusting Method for Storage Device

Compressor/decompressor circuits coupled with TDO-TMS/TDI die channel circuitry

Semiconductor integrated circuit

Structure for fractional-N phased-lock-loop (PLL) system

Fractional-N phased-lock-loop (PLL) system

Semiconductor integrated circuit and design automation system

TAP with control circuitry connected to device address port

Test device, test method and computer readable media

System and method for sharing a communications link between multiple communications protocols

Signal phase verification for systems incorporating two synchronous clock domains

Analog testing of ring oscillators using built-in self test apparatus

1149.1 tap linking modules

SEMICONDUCTOR INTEGRATED CIRCUIT

APPARATUS AND METHOD FOR TESTING ELECTRONIC SYSTEMS

Programmable test clock generation responsive to clock signal characterization

DDR register circuitry input to IC test controller circuitry

Interconnections for plural and hierarchical P1500 test wrappers

Test apparatus and test method with features of adjusting phase difference between data and reference clock and acquiring adjusted data

Computer-Based Method and System for Simulating Static Timing Clocking Results

Design for testability technique for phase detectors used in digital feedback delay locked loops

Structure for a duty cycle measurement circuit

Scan output connection in tap and scan test port

Local and global address compare with tap interface TDI/TDO lead

Absolute duty cycle measurement

JTAG bus communication method and apparatus

Propagation test strobe circuitry with boundary scan circuitry

INTEGRATED MARGIN TESTING

Design structure for a duty cycle measurement apparatus that operates in a calibration mode and a test mode

Apparatus for distributing a signal

MONITORING DEGRADATION OF CIRCIUT SPEED

Microcontroller for logic built-in self test (LBIST)

System and method for testing the accuracy of real time clocks

Variable delay circuit, testing apparatus, and electronic device

Shrink test mode to identify Nth order speed paths

Select signal and component override signal controlling multiplexing TDI/TDO

CIRCUIT TO PROVIDE TESTABILITY TO A SELF-TIMED CIRCUIT

Ring oscillator

High accuracy current mode duty cycle and phase placement sampling circuit

SEMICONDUCTOR INTEGRATED DEVICE

Frequency monitor

Optimized JTAG interface

Techniques for integrated circuit clock signal manipulation to facilitate functional and speed test

Clock distribution circuit and test method

System and Method of Multi-Frequency Integrated Circuit Testing

Address and TMS gating circuitry for TAP control circuit

Programmable clock control architecture for at-speed testing

Wafer scale testing using a 2 signal JTAG interface

Low phase noise clock generator for device under test

Semiconductor integrated circuit and method of testing same

TEST STANDARD INTERFACES AND ARCHITECTURES

Interface to full and reduce pin JTAG devices

IEEE 1149.1 and P1500 test interfaces combined circuits and processes

Serial I/O using JTAG TCK and TMS signals

Pulsed ring oscillator circuit for storage cell read timing evaluation

Semiconductor integrated circuit

On chip duty cycle measurement module

Debug circuit and a method of debugging

1114.9 tap linking modules

Capacitance measurement apparatus

ON-CHIP POWER SUPPLY MONITOR USING LATCH DELAY SENSOR

Built-in system and method for testing integrated circuit timing parameters

Semiconductor device, and test circuit and test method for testing semiconductor device

Measuring a long time period

Circuitry and method to measure a duty cycle of a clock signal

Method and system for measuring signal characteristics of data signals transmitted between integrated circuit chips

Sampling circuit and sampling method thereof

Scan Test Data Compression Method And Decoding Apparatus For Multiple-Scan-Chain Designs

Testable electronic circuit

Inspection support apparatus and inspection support method

Accurate integrated circuit performance prediction using on-board sensors

Test apparatus and test method

Consumption current balance circuit, compensation current amount adjusting method, timing generator, and semiconductor testing apparatus

Circuit timing monitor having a selectable-path ring oscillator

Testing apparatus for semiconductor device

Pulsed local clock buffer (LCB) characterization ring oscillator

System and method for verification and generation of timing exceptions

TAP domain selection circuit with AUXI/O1 or TDI lead

Test circuits having ring oscillators and test methods thereof

System and method for monitoring clock signal in an integrated circuit

Communication test circuit, communication interface circuit, and communication test method

Signal integrity measurement systems and methods using a predominantly digital time-base generator

DDR input interface to IC test controller circuitry

JTAG circuit transferring data between devices on TCK terminals

Apparatus and method for automatically self-calibrating a duty cycle circuit for maximum chip performance

Propagation test strobe circuitry with boundary scan circuitry

Clock circuits and counting values in integrated circuits

Semiconductor device, semiconductor device testing method, and probe card

TAP, ST, lockout, and IR SO enable output data control

Scan frame based test access mechanisms

APPARATUS, METHOD AND CIRCUIT FOR GENERATING CLOCK, AND APPARATUS, METHOD AND PROGRAM FOR VERIFYING OPERATION

Built-in system and method for testing integrated circuit timing parameters

Method and apparatus for measuring the relative duty cycle of a clock signal

Test apparatus for regulating a test signal supplied to a device under test and method thereof

Test semiconductor device in full frequency with half frequency tester

Duty cycle measurement method and apparatus that operates in a calibration mode and a test mode

Clock recovery system with triggered phase error measurement

Electronic device, circuit and test apparatus

Method and apparatus for on-chip duty cycle measurement

Phase linearity test circuit

Semiconductor integrated circuit device, measurement method therefore and measurement system for measuring AC characteristics thereof

Failure detection apparatus and failure detection method for a semiconductor apparatus

Generating masking control circuits for test response compactors

On-chip comparison and response collection tools and techniques

Multi-stage test response compactors

Scan testing using scan frames with embedded commands

Method of test of clock generation circuit in electronic device, and electronic device

Core wrappers with input and output linking circuitry

Variable delay circuit, recording medium, logic verification method and electronic device

Method for characterizing a bit detection event

HIGH SPEED BIST UTILIZING CLOCK MULTIPLICATION

Testing of multiple asynchronous logic domains

Microcontroller for logic built-in self test (LBIST)

Integrated circuit devices generating a plurality of drowsy clock signals having different phases

Built-in self test method for a digitally controlled crystal oscillator

Circuit and method for testing embedded phase-locked loop circuit

Testing combinational logic die with bidirectional TDI-TMS/TDO chanel circuit

Skew correction system eliminating phase ambiguity by using reference multiplication

Ring oscillator for determining select-to-output delay of a multiplexer

Self-test digital phase-locked loop and method thereof

Strobe technique for recovering a clock in a digital signal

INTEGRATION CIRCUIT AND TEST METHOD OF THE SAME

Flexible timebase for EYE diagram

Method for determining information about the internal workings of a chip based on electro-magnetic emissions therefrom

Utilizing clock shield as defect monitor

DUTY CYCLE MEASURMENT CIRCUIT FOR MEASURING AND MAINTAINING BALANCED CLOCK DUTY CYCLE

Apparatus and method for automatically self-calibrating a duty cycle circuit for maximum chip performance

Apparatus and method for controlling frequency of an I/O clock for an integrated circuit during test

Selectable JTAG or trace access with data store and output

Integrated circuit device

Semiconductor device and test system thereof

Clock transferring apparatus, and testing apparatus

Clock generation circuit

Testing with high speed pulse generator

Semiconductor chip and semiconductor integrated circuit device for relaying a reference clock from one hard macro to another

Methods and apparatus for managing clock skew between clock domain boundaries

Test circuit, delay circuit, clock generating circuit, and image sensor

BIST to provide phase interpolator data and associated methods of operation

Method and apparatus for source synchronous testing

System and method for information handling system clock source insitu diagnostics

Source synchronous timing extraction, cyclization and sampling

CLOCK CONTROL CIRCUIT FOR TEST THAT FACILITATES AN AT SPEED STRUCTURAL TEST

AC propagation testing preventing sampling test data at Capture-DR state

IC with linking module in series with TAP circuitry

Clock control of a multiple clock domain data processor

Controller receiving combined TMS/TDI and suppyling separate TMS and TDI

Clock jitter calculation device, clock jitter calculation method, and clock jitter calculation program

Debug and test system with format select register circuitry

Marginless status determination circuit

Shift clock generator, timing generator and test apparatus

Clock duty cycle based access timer combined with standard stage clocked output register

Method for at speed testing of multi-clock domain chips

Clock control circuit for test that facilitates an at speed structural test

Signals crossing multiple clock domains

Timing closure monitoring circuit and method

System and method for providing on-chip clock generation verification using an external clock

KVM switch configured to estimate a length of a conductor

Addressable tap domain selection circuit with selectable ⅗ pin interface

Addressable tap domain selection circuit with TDI/TDO external terminal

Method and system for testing distributed logic circuitry

High speed on chip testing

Utilizing clock shield as defect monitor

Internal clock generator

IC with TAP, STP and lock out controlled output buffer

Jitter applying circuit and test apparatus

Edge placement accuracy of signals generated by test equipment

Test clock generating apparatus

Utilizing clock shield as defect monitor

Delay lock circuit having self-calibrating loop

Delay lock circuit having self-calibrating loop

Interpolator testing system

General purpose delay logic

Automatic tuning of signal timing

System and method for maintaining device operation during clock signal adjustments

Device capable of detecting BIOS status for clock setting and method thereof

Digital frequency synthesis clocked circuits

Semiconductor device incorporating characteristic evaluating circuit operated by high frequency clock signal

Hierarchical link instruction register core/embedded core wrapper enable signals

Serial data I/O on JTAG TCK with TMS clocking

Source synchronous timing extraction, cyclization and sampling

Delay lock circuit having self-calibrating loop

Digital circuit for frequency and timing characterization

Microcomputer that does not cause destruction of peripherals

Compensation technique to mitigate aging effects in integrated circuit components

JTAG circuit transferring data between devices on TMS terminals

Apparatus for identification of locations of a circuit within an integrated circuit having low speed performance

System and method for debugging system-on-chips using single or n-cycle stepping

Variable-delay signal generators and methods of operation therefor

On-chip transistor degradation monitoring

Programmable jitter signal generator

Dynamic resynchronization of clocked interfaces

Method and apparatus for testing a bridge circuit

Channel with domain crossing

Circuits and methods for characterizing random variations in device characteristics in semiconductor integrated circuits

Semiconductor device having PLL-circuit

Wrapper instruction/data register controls from test access or wrapper ports

Jitter injection generator for measuring phase noise and jitter transfer function

Loopback testing of integrated circuits

Clock gating for power reduction during testing

Multiple clock and clock cycle selection for x-tolerant logic built in self test (XLBIST)

Method and apparatus for capture clock control to minimize toggling during testing

Analog built-in self-test scheme for high volume power management integrated circuit products

Method and system for debugging metastability in digital circuits

Method and system for managing transactions burstiness and generating signature thereof in a test environment

Split-scan sense amplifier flip-flop

Control data registers for scan testing

Clock shaper circuit for transition fault testing

Measuring input receiver thresholds using automated test equipment digital pins in a single shot manner

Save and restore register

Low cost design for test architecture

Self-tuning digital clock generator

Scan test control decoder with storage elements for use within integrated circuit (IC) devices having limited test interface

Measurement circuits for logic paths

Dynamically protective scan data control

Low pin count test controller

Devices and methods for test point insertion coverage

Debug mechanisms for a processor circuit

Dynamic debugging of circuits

Limited pin test interface with analog test bus

Multi-mode clock transmission network and method thereof

Runtime measurement of process variations and supply voltage characteristics

Binary signal generator