Up control, CSU circuit, scan circuit, up signal contact point

Multibit vectored sequential with scan

TCK to shift register and decompressor on shift-DR and pause-DR

Sleek serial interface for a wrapper boundary register (device and method)

Scan frame input register to decompressor parallel scan path outputs

Test circuits for monitoring NBTI or PBTI

Fine-grained speed binning in an accelerated processing device

Eye pattern generator

Scan chain operations

Test device for testing integrated circuit

Wafer with dio bidirectional lead, n dies, domains, clock leads

Electronic circuit including flip-flop using common clock

Inspection device

Apparatus and method for generating clock signal with low jitter and constant frequency while consuming low power

Tap, command, and router circuitry and asynchronous data register

Clock selection circuit and test clock generation circuit for LBIST and ATPG test circuit

Wrapper serial port externally accessible pin providing additional tap control

Signals on tap bi-directional TMS terminal selecting serial communication register

Method of measuring clock jitter, clock jitter measurement circuit, and semiconductor device including the same

On-chip frequency monitoring

Device throughput optimization for bus protocols

3D tap and scan port architectures

Tap gating scan register, comparator with expected data flip flop

Programmable scan shift testing

HIGHLY EFFICIENT DOUBLE-SAMPLING ARCHITECTURES

Scan output flip-flops

On-chip hardware-controlled window strobing

On-chip hardware-controlled window strobing

Input shift register having parallel serial scan outputs, command output

Separate output circuitry for tap, additional port, and port selector

Efficient test architecture for multi-die chips

Shadow protocol circuit producing enable, address, and address control signals

Debugging translation block and debugging architecture

Generating multiple pseudo static control signals using on-chip JTAG state machine

TCKC/TMSC counter, gating circuitry for selection, deselection, technology specific outputs

Method and device for testing a chain of flip-flops

Wafer tap domain die channel circuitry with separate die clocks

Logic built in self test circuitry for use in an integrated circuit with scan chains

Trace domain controller with test data I/O/control, internal control I/O

Vretention detector apparatus and method

Test circuit to debug missed test clock pulses

Test circuit capable of measuring PLL clock signal in ATPG mode

3D tap and scan port architectures

System and method for testing and configuration of an FPGA

Self test for safety logic

Test application time reduction using capture-per-cycle test points

Inputting TDI addresses when TDI high, moving update-DR to RT/I

Flip-flop circuit and scan chain using the same

Digital logic circuit for deterring race violations at an array test control boundary using an inverted array clock signal feature

Digital logic circuit for deterring race violations at an array test control boundary using an inverted array clock signal feature

CLOCK GATING CIRCUITS AND SCAN CHAIN CIRCUITS USING THE SAME

Apparatus and method for at-speed scan test

Organic light emitting display device and method of manufacturing the same

Boundary scan test system

Tap, decoder providing SC and SE to scan path circuits

Adapter circuitry with link and system interfaces to core circuitry

Lightweight, low overhead debug bus

Address/instruction registers, target domain interfaces, control information controlling all domains

Decompressed/compressed data parallel scan paths with input/output shift register, SCI/SCO

Testing circuit board with self-detection function and self-detection method thereof

Multi-stage test response compactors

Integrated circuit with an oscillating signal-generating assembly

Internal circuit TMS input, FIFO coupled to parallel-input serial-output register

HIGHLY EFFICIENT DOUBLE-SAMPLING ARCHITECTURES

TMS pin for mode signal and output for read data

Scan path only one-bit scan register when component not selected

Two signal JTAG with TLM, scan domain and diagnostics domain

Tap domain selection circuit with AUX buffers and multiplexer

Decompressed/compressed data parallel scan paths with tap decoded shift/scan clocks

Clock selection circuit and test clock generation circuit for LBIST and ATPG test circuit

APPARATUS AND METHOD FOR EMPLOYING MUTUALLY EXCLUSIVE WRITE AND READ CLOCK SIGNALS IN SCAN CAPTURE MODE FOR TESTING DIGITAL INTERFACES

Self test for safety logic

Inverted TCK, input and fixed address registers, comparator, compare register

Tap linking module, first and second taps, input/output linking circuitry

Generating multiple pseudo static control signals using on-chip JTAG state machine

TAP and gating enable, CaptureDR, capture, and gated CaptureDR signals

Logic built-in self-test (LBIST) with pipeline scan enable launch on shift (LOS) flip-flop circuit

Semiconductor power and performance optimization

Stuck-at fault detection on the clock tree buffers of a clock source

Taps with TO-T2, T4 classes with, without topology selection logic

Method and system for determining the dynamic consumption of a module within an electronic device such as a system on chip

Test circuit to isolate HCI degradation

Built-in device testing of integrated circuits

Scan logic for circuit designs with latches and flip-flops

Wide-range clock signal generation for speed grading of logic cores

Integrated system and method for testing system timing margin

One tap domain coupling two trace circuits, address command port

Scan input stimulus registers, test control register controlling compressor circuitry

Dual port tap router for asynchronous capture shift data register

Differential I/O for parallel scan paths, scan frames, embedded commands

Die top, bottom parallel/serial date with test and scan circuitry

Reconfigurable test access port with finite state machine control

Vretention detector apparatus and method

Clock path technique for using on-chip circuitry to generate a correct encode pattern to test the on-chip circuitry

Clock path technique for using on-chip circuitry to generate a correct encode pattern to test the on-chip circuitry

Ultra-fast autonomous clock monitoring circuit for safe and secure automotive applications

First, second access ports and selector with separate output circuitry

Scan chain latch design that improves testability of integrated circuits

Double data rate circuitry coupled to test access mechanisms, controller

Control I/O coupling scan test port to test access port

Method and device for testing a chain of flip-flops

Tap flip flop, gate, and compare circuitry on rising SCK

Shadow protocol detection, address circuits with command shift, update registers

Logic built in self test circuitry for use in an integrated circuit with scan chains

Multi-chassis test device and test signal transmission apparatus of the same

Logic built in self test circuitry for use in an integrated circuit with scan chains

Logic built in self test circuitry for use in an integrated circuit with scan chains

DYNAMICALLY CONFIGURABLE SHARED SCAN CLOCK CHANNEL ARCHITECTURE

HIGHLY EFFICIENT DOUBLE-SAMPLING ARCHITECTURES

Clock gating for X-bounding timing exceptions in IC testing

Serial test core wrapper link instruction register with resynchronization register

Receiving addresses on moving TLR to R/TI when TDI high

Status register between test data I/O of scan port SUT

Scan Logic For Circuit Designs With Latches And Flip-Flops

Addressable test access port domain selection circuitry TCK logic gate

Sleek serial interface for a wrapper boundary register (device and method)

Two signal JTAG wafter testing bist and scan tap domains

Adapter circuitry with global bypass register, legacy test data, multiplexer

Clock verification

Serial I/O communication control signals coupled to tap control signals

Scan chain circuits in non-volatile memory

Auto test grouping/clock sequencing for at-speed test

Scan chain latch design that improves testability of integrated circuits

Test point circuit, scan flip-flop for sequential test, semiconductor device and design device

Interleaver ic with up control and capture, shift, update circuitry

Gating tap register control bus and auxiliary/wrapper test bus

Reducing power requirements and switching during logic built-in-self-test and scan test

High speed interconnect circuit test method and apparatus

Semiconductor circuit and semiconductor system

Addressable tap domain selection circuit with instruction and linking circuits

TCK, TMS(C) clock, gating circuitry providing selection and deselection outputs

Taps of different scan classes with, without topology selection logic

Tap SPC with tap state machine reset and clock control

TAP and auxiliary circuitry with auxiliary output multiplexer and buffers

Organic light emitting display device and method of manufacturing the same

Address-command port connected to trace circuits and tap domains

Tap, CMD with two flip-flops, routing circuit, and data register

TMS serial communication circuitry coupled to tap IR enable output

On-the-fly test and debug logic for ATPG failures of designs using on-chip clocking

Tuning a testing apparatus for measuring skew

Tuning a testing apparatus for measuring skew

Multi-bit flip-flops and scan chain circuits

Self-test circuit in integrated circuit, and data processing circuit

Clock generation circuit that tracks critical path across process, voltage and temperature variation

Method and apparatus for generating featured test pattern

Method and apparatus for test time reduction using fractional data packing

DAP local, group, and global control of TAP TCK

Scan testing scan frames with embedded commands and differential signaling

Dynamic Clock Chain Bypass

Scan flip-flop circuit with dedicated clocks

Apparatus and method for measuring power supply noise

Multi-stage test response compactors

IC and process shifting compressed data and loading scan paths

Tap controller state machine scanning capturing plurality of scan paths

Taps with class T0-T2, T4 capabilities and topology selection logic

Multichip package link

Semiconductor device, electronic device, and self-diagnosis method for semiconductor device

Method and system for digital circuit scan testing

Full/reduced pin JTAG interface shadow protocol detection, command, address circuits

Decompressed/compressed data parallel scan paths with input/output shift register, SCI/SCO

Systems and methods for concurrently testing master and slave devices in a system on a chip

Third tap circuitry controlling linking first and second tap circuitry

Chip performance monitoring system and method

Tap decay test circuitry having capture test strobe enable input

TAP gated updateDR output AUX test control of WSP update

Embedded parallel scan paths, stimulus formatter, and control interface circuitry

Test mode circuit and semiconductor device including the same

Low-overhead debug architecture using a speculative, concurrent and distributed data capture and propagation scheme

IC decompress and maskable compress TAM with SFIR and SFCR

TMS/TDI and SIPO controller circuitry with tap and trace interfaces

Taps with class T0-T2 and T3, T4(W), and T5(W) capabilities

Test circuit and method of controlling test circuit

Tap clock and enable control of scan register, flip-flop, compressor

Cycle accurate and cycle reproducible memory for an FPGA based hardware accelerator

High-speed flip-flop with robust scan-in path hold time

Packet tracking in a verification environment

Testbench builder, system, device and method with phase synchronization

Testbench builder, system, device and method including a generic monitor and transporter

Testbench builder, system, device and method having agent loopback functionality

Testbench builder, system, device and method

Testbench builder, system, device and method including latency detection

Mixing of low speed and high speed clocks to improve test precision of a digital integrated circuit

Multiple-capture DFT method for detecting or locating crossing clock-domain faults during self-test or scan-test

Circuit for testing integrated circuits

System internal latency measurements in realtime applications

Circuit techniques for efficient scan hold path design

Testing apparatus for electronic device

TCK/TMS(C) counter circuitry with third, fourth count and reset outputs

Scan chain latch design that improves testability of integrated circuits

SYSTEM AND METHOD FOR ELIMINATING INDETERMINISM IN INTEGRATED CIRCUIT TESTING

Semiconductor apparatus and test device therefor

Mixed mode integrated circuit, method of providing a controllable test clock signal to a sub-circuitry of the mixed-mode integrated circuit and method of detecting current paths causing violations of electromagnetic compatibility standards in the mixed mode integrated circuit

Period measuring circuit and semiconductor device including the same

Test circuit and test method of semiconductor apparatus

Integrated circuit with distributed clock tampering detectors

Sequential circuit with error detection

Functional testing of an integrated circuit chip

Scan test multiplexing

Scan test multiplexing

Integrated circuit device and method therefor

Integrated circuit testing

Duty cycle based timing margining for I/O AC timing

Integrated circuit control based on a first sample value and a delayed second sample value

Scan-based MCM interconnect testing

Multiple-capture DFT system for detecting or locating crossing clock-domain faults during scan-test

Method and control device for launch-off-shift at-speed scan testing

At-speed test of memory arrays using scan

Testing I/O timing defects for high pin count, non-contact interfaces

Method and apparatus for test time reduction using fractional data packing

Monitoring on-chip clock control during integrated circuit testing

Multiple-capture DFT system for detecting or locating crossing clock-domain faults during scan-test

CHIP INSTRUMENTATION FOR IN-SITU CLOCK DOMAIN CHARACTERIZATION

Measuring setup and hold times using a virtual delay

Method and apparatus for performing de-skew control

Clock verification

Method and apparatus for valid encoding

Degradation detector and method of detecting the aging of an integrated circuit

Hybrid on-chip clock controller techniques for facilitating at-speed scan testing and scan architecture support

System and method for reducing voltage drop during automatic testing of integrated circuits

Handling slower scan outputs at optimal frequency

In situ on the fly on-chip variation measurement

Automated test system with event detection capability

Circuit for testing integrated circuits

Position-measuring device and method for testing a clock signal

Apparatus for at-speed testing, in inter-domain mode, of a multi-clock-domain digital integrated circuit according to BIST or SCAN techniques

Device and method for generating input control signals of a serialized compressed scan circuit

Clock generation circuit that tracks critical path across process, voltage and temperature variation

Clock jitter and power supply noise analysis

Scan or JTAG controllable capture clock generation

HIGH RESOLUTION CURRENT PULSE ANALOG MEASUREMENT

System and method for measuring an integrated circuit age

Built-in self test (BIST) with clock control

Self-testing integrated circuits

On-chip controller and a system-on-chip

On-chip spectral analysis using enhanced recursive discrete Fourier transforms

Sequential circuit with error detection

Analysis method for signal time margin

Circuit test system electric element memory control chip under different test modes

SYSTEM FOR TESTING REAL TIME CLOCK

Methods and structure for correlation of test signals routed using different signaling pathways

Cycle accurate and cycle reproducible memory for an FPGA based hardware accelerator

Oscillation circuit, integrated circuit, and abnormality detection method

IEEE1588 protocol negative testing method

Integrated circuit device, electronic device and method for detecting timing violations within a clock signal

IC with wrapper, TAM, TAM controller, and DDR circuitry

Test access and scan test ports with lockout signal terminal

Integrated circuit testing module including signal shaping interface

Data source, destination and input/output circuit with multiplexer and flip-flop

BIST circuit for phase measurement

Address and command port connecting trace circuitry and TAP domain

Access port selector and gating selecting test access port

Tap with address, state monitor and gating circuitry

TAP test clock control circuitry connected to device address port

Parallel scan paths with stimulus and header data circuitry

Wrapper selection circuits with selection and enable inputs

Semiconductor device on which wafer-level burn-in test is performed and manufacturing method thereof

Advanced/enhanced protocol circuitry connected to TCK, TMS, and topology circuitry

TDI multiplexer gating controlled by override selection logic

Master reset and synchronizer circuit with data and clock inputs

IR output of mode-1 and ATC enable; ATC gating of shift-1

DOUBLE DATA RATE TEST INTERFACE AND ARCHITECTURE

Scan register and flip-flop alternately receiving SDI and mask data

JTAG shadow protocol circuit with detection, command and address circuits

High speed test circuit and method

Microcontroller for logic built-in self test (LBIST)

Bi-directional TMS lead carrying TMS and frame data in/out signals

Scan-based MCM interconnecting testing

Address and instruction controller with TCK, TMS, address match inputs

SELECTABLE JTAG OR TRACE ACCESS WITH DATA STORE AND OUTPUT

Receiving apparatus, test apparatus, receiving method and test method

DF/dT trigger system and method

TEST ACCESS PORT WITH ADDRESS AND COMMAND CAPABILITY

Circuits and Methods for Characterizing Random Variations in Device Characteristics in Semiconductor Integrated Circuits

Apparatus for at-speed testing, in inter-domain mode, of a multi-clock-domain digital integrated circuit according to BIST or SCAN techniques

Data register control from TAP+ATC or discrete WSP signals

Debug access with programmable return clock

Tap interface select circuit with AUX1/02-TMS and TMS/RCK-RCK leads

Adapter leads connected to test circuitry and third leads set

TAP with serial I/O coupled to TCK

Method and system for providing efficient on-product clock generation for domains compatible with compression

Programmable test compression architecture with serial input register and multiplexer

Methods and systems for production testing of DCO capacitors

AT speed TAP with dual port router and command circuit

Methods and structure for on-chip clock jitter testing and analysis

Multiplexer input linking circuitry to IC and core TAP domains

Tap and scan test port with IR lock out output

Scan or JTAG controllable capture clock generation

Multiplexer for tap controller and WSP controller outputs

Apparatus and system for implementing variable speed scan testing

Inverted TCK access port selector with normal TCK data flip-flop

System and method for setting counter threshold value

Circuit for testing integrated circuits

Device address port circuitry with local, group, and global outputs

Compare circuit having inputs from scan registers and flip-flops

Link instruction register with resynchronization register

Scan paths, stimulus, and header circuitry with command/frame marker outputs

Clock controller for JTAG interface

Flexible timebase for eye diagram

TAP interface select circuit with TMS/RCK or RCK lead

Die with DIO path, clock input, TLM, and TAP domains