CLOCK TAMPER DETECTOR AND METHOD FOR DETECTING A CLOCK TAMPERING EVENT

ISOCHRONOUS PHASE-DRIFT TRACKING SYSTEM

SYSTEM ON CHIP AND DEBUGGING METHOD FOR SYSTEM ON CHIP

VOLTAGE DROOP MITIGATION DURING AUTOMOTIVE ELECTRONICS BUILT IN SELF TEST

ELECTRONIC CIRCUIT AND METHOD OF ERROR CORRECTION

HIGH SPEED COMPARATOR BASED SUPPLY GLITCH DETECTOR

VOLTAGE GLITCH DETECTION

CLOCK GLITCH DETECTION CIRCUIT AND METHOD THEREOF

CIRCUIT FOR MEASURING DUTY CYCLE DISTORTION

I3C ERROR STATES TEST STRATEGY

CLOCK GATING CLONING IN DESIGN FOR TEST PRACTICE

JITTER INJECTION GENERATOR FOR MEASURING PHASE NOISE AND JITTER TRANSFER FUNCTION

TEST APPARATUS, TEST METHOD, AND PROGRAM

COMPARATOR BUILT-IN SELF TEST (BIST) CIRCUIT

APPARATUS AND METHODS FOR JITTER TESTING OF CLOCK SIGNALS

REAL-TIME DEBUG IN LOW-POWER DEVICES

Testing a Comparator Circuit

CIRCUIT AND METHOD FOR INTERCONNECT TEST

JTAG-BASED APPARATUS AND METHOD FOR INPUT CLOCK FREQUENCY MEASUREMENT

JITTER SENSOR CIRCUIT

SYSTEM AND METHOD FOR DESIGNING CLOCK MANAGEMENT UNIT USING A NO-CODE APPROACH

FLEXIBLE PATTERN TESTING FOR D2D LINK PATHS

CONTROLLER AREA NETWORK SYSTEM WITH IN-SYSTEM CONFIGURATION

TEST AND/OR MEASUREMENT SYSTEM

TEST AND/OR MEASUREMENT INSTRUMENT FOR MEASURING AN ELECTRICAL SIGNAL

ELECTRONIC CIRCUIT FOR TEST OF DIGITAL CIRCUIT

TEST AND/OR MEASUREMENT SYSTEM

ANALOG ENVIRONMENTAL MONITORING CIRCUITS AND METHODS

Process Corner Simulation System Capable of Processing a Duty Cycle and Speed-based Process Corner Simulations

TIME-ALIGNED RF ANALYSIS FROM GEOGRAPHICALLY DISTRIBUTED RECEIVERS

Latchup Detector and Clock Loss Detector

METHOD FOR CHECKING AT LEAST ONE FIRST CLOCK GENERATOR OF A FIRST FIELD DEVICE IN A PROCESS MEASURING SYSTEM

DEVICES AND METHODS FOR TESTING DIES WITH OFF-DIE CLOCKS

Device and Method for Measuring a Duty Cycle of a Clock Signal

Apparatus and Method for Clock Frequency Estimation With Subsets of Time Measurements

Apparatus and Method for Clock Frequency Estimation With Delayed Measurements

CLOCK CONVERSION DEVICE, TEST SYSTEM INCLUDING THEREOF AND METHOD OF OPERATING THE TEST SYSTEM

TESTING CIRCUIT

DEVICE ACCESS PORT SELECTION

CHIP AND CHIP TESTING METHOD

Supply Chain Security for Chiplets

APPARATUSES AND METHODS FOR JITTER MEASUREMENT

METHOD OF MONITORING A CLOCK SIGNAL

AT-SPEED TEST ACCESS PORT OPERATIONS

SYSTEM FOR AUTOMATED DATA RETRIEVAL FROM AN INTEGRATED CIRCUIT FOR EVENT ANALYSIS

SYSTEM AND METHOD FOR GENERATING CLOCK PULSES FOR AT-SPEED TESTING OF INTEGRATED CIRCUITS

CLOCK SYNCHRONIZATION CIRCUIT

FAILURE DETECTION CIRCUIT, SEMICONDUCTOR DEVICE AND FAILURE DETECTION METHOD

TESTING MULTI-CYCLE PATHS BASED ON CLOCK PATTERN

3D TAP & SCAN PORT ARCHITECTURES

DATA CORRECTION AND PHASE OPTIMIZATION IN HIGH-SPEED RECEIVERS

APPARATUSES AND METHODS FOR FACILIATATING A DYNAMIC CLOCK FREQUENCY FOR AT-SPEED TESTING

Diagnosing Identical Circuit Blocks in Data Streaming Environment

INTERFACE TO FULL AND REDUCED PIN JTAG DEVICES

DEVICE, METHOD AND SYSTEM FOR IN-FIELD LANE TESTING AND REPAIR WITH A THREE-DIMENSIONAL INTEGRATED CIRCUIT

CLOCK GATING CIRCUITS AND METHODS FOR DUAL-EDGE-TRIGGERED APPLICATIONS

TEST-TIME OPTIMIZATION WITH FEW SLOW SCAN PADS

FULLY DIGITAL DOMAIN INTEGRATED FREQUENCY MONITOR

SELECTABLE JTAG OR TRACE ACCESS WITH DATA STORE AND OUTPUT

SYSTEM AND METHOD FOR DETECTING FAULTS IN INTEGRATED CIRCUITS

ADDRESSABLE TEST ACCESS PORT

ELECTRONIC CIRCUIT AND METHOD OF ERROR CORRECTION

CLUSTERING CLOCK CHAIN DATA FOR TEST-TIME REDUCTION

DEVICE FOR MEASURING FREQUENCY RESPONSE OF A WAFER

Clock gating circuits and methods for dual-edge-triggered applications

Integrated circuit with timing correction circuitry

Machine Learning Control of Clock Drift

PROGRAMMABLE TEST COMPRESSION ARCHITECTURE INPUT/OUTPUT SHIFT REGISTER

LOW POWER AND AREA CLOCK MONITORING CIRCUIT USING RING DELAY ARRANGEMENT

SEMICONDUCTOR INTEGRATED CIRCUIT AND TEST METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT

INTEGRATED CIRCUIT AND INTEGRATED CIRCUIT TESTING METHOD

TEST AID UNITS

SYSTEM AND METHOD FOR CONTROLLING AT-SPEED TESTING OF INTEGRATED CIRCUITS

ACCURATE CLOCK EDGE CALIBRATION OVER PVT CORNERS

ACCURATE CLOCK CALIBRATION FOR DIE-TO-DIE (D2D) INTERFACES

Low-frequency oscillator monitoring circuit

TIMING MARGIN SENSOR

METHOD FOR MONITORING A CLOCK GENERATOR MODULE OF AN ELECTRONIC CIRCUIT

Latchup Detector and Clock Loss Detector

Clock recovery unit adjustment

DETERMINATION DEVICE, TEST SYSTEM, AND GENERATION DEVICE

Test device for testing on-chip clock controller having debug function

SOC-oriented concurrent test system for multiple clock domains and test method thereof

DISPLAY DEVICE, PANEL DEFECT DETECTION CIRCUIT AND PANEL DEFECT DETECTION METHOD

SEMICONDUCTOR CHIP AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME

Oscillator And Electronic Device

Time-to-digital converter circuit with self-testing function

SELF-RESET TESTING SYSTEMS AND METHODS

SPUR CANCELLATION FOR SPUR MEASUREMENT

Design For Test For Source Synchronous Interfaces

Clock Insertion Delay Systems and Methods

CLOCK MONITORING CIRCUIT

SEMICONDUCTOR DEVICE, VEHICLE-MOUNTED APPLIANCE, AND CONSUMER APPLIANCE

TRANSMITTER FOR ULTRA-HIGH SPEED AND STORAGE DEVICE INCLUDING THE SAME

Semiconductor device, debug system, and debug method

COMPETING PATH RING-OSCILLATOR FOR DIRECT MEASUREMENT OF A LATCH TIMING WINDOW PARAMETERS

SEMICONDUCTOR DEVICE AND METHOD OF SCAN TEST FOR THEREOF

DETERMINATION DEVICE, TEST SYSTEM, AND GENERATION DEVICE

Test device for testing on-chip clock controller having debug function

Electronic device and method for performing clock gating in electronic device

SENSOR MODULE

Flexible one-hot decoding logic for clock controls

MEMORY, MEMORY SYSTEM AND METHOD OF CONTROLLING STORAGE DEVICE

ANALOG PHASE SELECTION TEST SYSTEM

Systems and techniques for timing mismatch reduction

Electronic device for self-testing period of clock signal and monitoring method thereof

At-speed test access port operations

Methods for determining and calibrating non-linearity in a Phase Interpolator and related devices and systems

Electronic device and phase detector

Electronic device and phase detector

TEST CIRCUIT, TEST METHOD, AND COMPUTING SYSTEM COMPRISING TEST CIRCUIT

Configuration of configurable test logic

Selectable JTAG or trace access with data store and output

SCAN CIRCUIT AND METHOD

Scan testing using scan frames with embedded commands

Signal generation device, measurement device, and method

3D tap and scan port architectures

Device and method for measuring a duty cycle of a clock signal

Addressable test access port

Frequency-detecting circuit, duty-cycle corrector, and electronic device

SCAN TESTING USING SCAN FRAMES WITH EMBEDDED COMMANDS

Method and circuit for performing error detection on a clock gated register signal

Method and circuit for performing error detection on a clock gated register signal

Electronic circuit and method of error correction

Integrated circuit chip testing interface with reduced signal wires

Determining charge pump efficiency using clock edge counting

Test access port with address and command capability

Detection circuit of clock anomaly and method, clock circuit, chip and radar

Testing system and testing method

Integrated functional and design for testability (DFT) clock delivery architecture

Data correction and phase optimization in high-speed receivers

Device access port selection

Scan frame based test access mechanisms

ICG TEST COVERAGE WITH NO TIMING OVERHEAD

System and method for testing clocking systems in integrated circuits

Interface to full and reduced pin JTAG devices

Fast clock detection

Clock shaper circuit for transition fault testing

Scan chain for memory with reduced power consumption

AT-speed test access port operations

Programmable test compression architecture input/output shift register coupled to SCI/SCO/PCO

Wafer scale testing using a 2 signal JTAG interface

3D TAP and scan port architectures

Test circuit using clock gating scheme to hold capture procedure and bypass mode, and integrated circuit including the same

Clock monitor circuit and microcontroller and control method thereof

TECHNIQUE FOR ENABLING ON-DIE NOISE MEASUREMENT DURING ATE TESTING AND IST

System on chip for performing scan test and method of designing the same

System, apparatus and method for identifying functionality of integrated circuit via clock signal superpositioning

Detection circuit and detection method

TECHNIQUES FOR IDENTIFICATION AND CORRECTION OF CLOCK DUTY-CYCLE

Detection circuit for detecting the amplitude of a clock signal and detection method thereof

SEMICONDUCTOR INTEGRATED CIRCUIT, A METHOD FOR TESTING THE SEMICONDUCTOR INTEGRATED CIRCUIT, AND A SEMICONDUCTOR SYSTEM

Performing testing utilizing staggered clocks

Built in self test (BIST) for clock generation circuitry

METHODS AND SYSTEMS FOR AUTOMATIC WAVEFORM ANALYSIS

Oscillation period detection circuit and method, and semiconductor memory

Reduced signaling interface method and apparatus

Self-contained built-in self-test circuit with phase-shifting abilities for high-speed receivers

Integrated circuit including test circuit and method of manufacturing the same

Multi-die debug stop clock trigger

Test method for delay circuit and test circuitry

Time offset method and device for test signal

Clock anomaly detection with dynamic calibration

DEBUG SYSTEM AND DEBUG METHOD

Apparatus for device access port selection

Clock conversion device, test system having the same, and method of operating test system

Baseboard management controller (BMC) test system and method

Systems and methods for fault detection and reporting through serial interface transceivers

Test element group and test method

Method and circuit for simple measurement of the phase shift between two digital clock signals having the same frequency

SEMICONDUCTOR DEVICE AND CLOCK CONTROL METHOD

REAL-EQUIVALENT-TIME FLASH ARRAY DIGITIZER OSCILLOSCOPE ARCHITECTURE

Generating multiple pseudo static control signals using on-chip JTAG state machine

Scan test control decoder with storage elements for use within integrated circuit (IC) devices having limited test interface

Deskew cell for delay and pulse width adjustment

Circuit for transferring data from one clock domain to another

Low power flip-flop

Scan circuit and method

Semiconductor integrated circuit device and operating method thereof

High speed integrated circuit testing

Transition fault testing of functionally asynchronous paths in an integrated circuit

At-speed test access port operations

Circuits And Methods For Configurable Scan Chains

Implementing a JTAG device chain in multi-die integrated circuit

Method and apparatus for power measurement in electronic circuit design and analysis

Scan frame based test access mechanisms

Method and apparatus for on-chip power metering using automated selection of signal power proxies

CFAR OS detection hardware with two sets of comparators

Selectable JTAG or trace access with data store and output

High speed debug-delay compensation in external tool

Calibration circuit, memory and calibration method

Wafer scale testing using a 2 signal JTAG interface

3D tap and scan port architectures

Core partition circuit and testing device

Fault injection in a clock monitor unit

Automatic fault injection in a clock monitor unit

Device and method for measuring characteristics of a wafer

Spur cancellation for spur measurement

Programmable test compression architecture input/output shift register coupled to SCI/SCO/PCO

Memory embedded full scan for latent defects

Test access port with address and command capability

Detection circuit and detection method

Addressable test access port apparatus

Device for detecting margin of circuit operating at certain speed

Scan testing using scan frames with embedded commands

Duty cycle detector self-testing

Scan test device and scan test method

Interface to full and reduced pin JTAG devices

Scan output flip-flop with power saving feature

Integrated circuit with reduced signaling interface

Temporal jitter analyzer and analyzing temporal jitter

Implementing a JTAG device chain in multi-die integrated circuit

Systems and methods for fault detection and reporting through serial interface transceivers

Semiconductor device for controlling supply of clock signal

Multibit vectored sequential with scan

Determining a voltage and/or frequency for a performance mode

Method for testing device under test and apparatus using the same

Electronic circuit and corresponding method of testing electronic circuits

JTAG bus communication method and apparatus

True single phase clock (TSPC) pre-charge based flip-flop

Apparatus for device access port selection

Signal analysis method and measurement instrument

Test method and test system

Boundary test circuit, memory and boundary test method

Self test for safety logic

Heterogeneous-computing based emulator

Semiconductor device and burn-in test method thereof

Zero-pin test solution for integrated circuits

3D tap and scan port architectures

Tap, command, router circuitry, and data register

Wafer scale testing using a 2 signal JTAG interface

Reduced signaling interface circuit

Programmable test compression architecture input/output shift register coupled to SCI/SCO/PCO

Test access port with address and command capability

Scan test control decoder with storage elements for use within integrated circuit (IC) devices having limited test interface

Test access port with address and command capability

Selectable JTAG or trace access with data store and output

Device with a plurality of clock domains

Automated test equipment for testing high-power electronic components

Method and a circuit for adaptive regulation of body bias voltages controlling NMOS and PMOS transistors of an IC

Digital measurement circuit and memory system using the same

Data transmission code and interface

Generating multiple pseudo static control signals using on-chip JTAG state machine

Detection device and detection method

Method for reducing power consumption in scannable flip-flops without additional circuitry

System and method for electronics timing delay calibration

Method for automatically testing processor

Built-in self-test in a data processing apparatus

Scan frame based test access mechanisms

Real-time clock module, electronic device and vehicle

Programmable test compression architecture input/output shift register coupled to SCI/SCO/PCO

Time interleaved scan system

Semiconductor device including clock generation circuit

Watchdog built in test (BIT) circuit for fast system readiness

Testing device and testing method for testing a device under test

Information processing apparatus and control method

IC test architecture having differential data input and output buffers

Chain testing and diagnosis using two-dimensional scan architecture

At-speed test access port operations

Multibit vectored sequential with scan

Count value generation circuit, physical quantity sensor module, and structure monitoring device

Testing of integrated circuits during at-speed mode of operation

Digital logic circuit for deterring race violations at an array test control boundary using an inverted array clock signal feature

Channel circuitry, tap linking module, scan tap, debug tap domains

Chip

Two pin scan interface for low pin count devices

Serial data communication modes on TDI/TDO, receive TMS, send TMS

3D tap and scan port architectures

TEST CIRCUIT AND TEST METHOD

Semiconductor device

TAP gating scan enable output to decompressor and scan registers

Cycle accurate and cycle reproducible memory for an FPGA based hardware accelerator

Data reading device and data reading method for design-for-testing

Oscillator, electronic device, and vehicle

Oscillator, electronic device, and vehicle

Spur cancellation for spur measurement

Switching FPI between FPI and RPI from received bit sequence

On-chip spread spectrum characterization

Boundary scan and wrapper circuitry with state machine and multiplexers

Method of measuring clock jitter, clock jitter measurement circuit, and semiconductor devices including the same

Access ports, port selector with enable outputs, and TDI/TDO multiplexer

Organic light emitting display device and method of manufacturing the same

Count value generation circuit, physical quantity sensor module, and structure monitoring device

Operating addressable circuit inputting separate data/address signals from data input apparatus

Clock verification

Crosstalk generation and detection for digital isolators

Semiconductor device including clock generation circuit

Entering home state after soft reset signal after address match

Functional, tap, trace circuitry with multiplexed tap, trace data output

Semiconductor device

Adaptive voltage scaling using temperature and performance sensors

System and method for testing and configuration of an FPGA

On-chip clock control monitoring

Semiconductor device

Transistion fault testing of funtionally asynchronous paths in an integrated circuit

First, second test domains and test mode select control circuitry

Digital measurement circuit and memory system using the same

Oscillator, clock signal generator, electronic apparatus, and vehicle

Tap, counter storing value of serial access by communication circuitry

IC receiving TDI addresses in R/TI after update-IR while TDI in second logic state