171870 ⎘
Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere; Testing of electronic circuits, e.g. by signal tracer; Testing of digital circuits; Functional testing; Reconfiguring for testing, e.g. LSSD, partitioning Test of Combinational circuits
Automatic test pattern generation-based circuit verification method and apparatus
#2Pseudo-random binary sequences (PRBS) generator for performing on-chip testing and a method thereof
#3Test circuit
#4Failure diagnostic apparatus and failure diagnostic method
#5Method of high speed and dynamic configuration of a transceiver system
#6Dynamic weight selection process for logic built-in self test
#7High-impedance fault detection using wireless current transformers
#8Apparatus, method, and system for testing IC chip
#9Method for managing the operation of a circuit with triple modular redundancy and associated device
#10System and method for packet communication
#11Method and device for multi-dimensional processing using a single-state decision feedback equalizer
#12Multi-pair gigabit ethernet transceiver
#13PHY control module for a multi-pair gigabit transceiver
#14Multi-pair gigabit ethernet transceiver having adaptive disabling of circuit elements
#15System and method for high-speed decoding and ISI compensation in a multi-pair transceiver system
#16LOGIC CIRCUIT MODEL VERIFYING METHOD AND APPARATUS
#17Demodulator for a multi-pair gigabit transceiver
#18DYNAMIC REGULATION OF POWER CONSUMPTION OF A HIGH-SPEED COMMUNICATION SYSTEM
#19High-speed decoder for a multi-pair gigabit transceiver
#20Physical coding sublayer for a multi-pair gigabit transceiver
#21Multi-pair gigabit Ethernet transceiver
#22Analog testing of ring oscillators using built-in self test apparatus
#23Multi-pair gigabit ethernet transceiver
#24Test method and test program of semiconductor logic circuit device
#25System and method for high-speed decoding and ISI compensation in a multi-pair transceiver system
#26PHY control module for a multi-pair gigabit transceiver
#27System and method for trellis decoding in a multi-pair transceiver system
#28Generating device, generating method, program and recording medium
#29Conversion device, conversion method, program, and recording medium
#30Double-edge triggered scannable pulsed flip-flop for high frequency and/or low power applications
#31Dynamic regulation of power consumption of a high-speed communication system
#32Multi-pair gigabit ethernet transceiver
#33DOUBLE-EDGE TRIGGERED SCANNABLE PULSED FLIP-FLOP FOR HIGH FREQUENCY AND/OR LOW POWER APPLICATIONS
#34Method for performing a test case with a LBIST engine on an integrated circuit, integrated circuit and method for specifying an integrated circuit
#35Multi-pair gigabit ethernet transceiver
#36Multi-pair gigabit ethernet transceiver having a single-state decision feedback equalizer
#37Multi-pair gigabit ethernet transceiver having decision feedback equalizer
#38Multi-pair gigabit Ethernet transceiver having adaptive disabling of circuit elements
#39Timing recovery system for a multi-pair gigabit transceiver
#40Semiconductor integrated circuit device, method of testing the same, database for design of the same and method of designing the same
#41High-speed decoder for a multi-pair gigabit transceiver
#42System and method for high-speed decoding and ISI compensation in a multi-pair transceiver system
#43Dynamic register with IDDQ testing capability
#44PHY control module for a multi-pair gigabit transceiver
#45Physical coding sublayer for a multi-pair gigabit transceiver
#46Pair-swap independent trellis decoder for a multi-pair gigabit transceiver
#47PHY control module for a multi-pair gigabit transceiver
#48Ethernet transceiver with single-state decision feedback equalizer
#49Dynamic regulation of power consumption of a high-speed communication system
#50Dynamic register with IDDQ testing capability