171872 ⎘
Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere; Testing of electronic circuits, e.g. by signal tracer; Testing of digital circuits; Functional testing; Reconfiguring for testing, e.g. LSSD, partitioning; Test of Modular systems, e.g. Wafers, MCM's Board Level Test, e.g. P1500 Standard
BOUNDARY SCAN FOR SHARED ANALOG AND DIGITAL PINS
#2Apparatus and Method for Testing Semiconductor Devices
#33D STACKED DIE TEST ARCHITECTURE
#4Methods and apparatus to implement a boundary scan for shared analog and digital pins
#5Test system, test method, and non-transitory computer readable medium
#63D stacked die test architecture
#73D stacked die test architecture
#8METHOD AND DEVICE FOR TESTING INTEGRATED CIRCUIT
#9Apparatus and Method for Testing Semiconductor Devices
#10Core partition circuit and testing device
#113D stacked die test architecture
#12Method of and an arrangement for analyzing manufacturing defects of multi-chip modules made without known good die
#13IC first/second surfaces contact points, test control port, parallel scan
#14Boundary scan and wrapper circuitry with state machine and multiplexers
#15Sleek serial interface for a wrapper boundary register (device and method)
#16Tap Dual Port Router, First, Second Multiplexer, First, Second Gating
#17Wrapper serial port externally accessible pin providing additional tap control
#18Component communications in system-in-package systems
#19Test mode isolation and power reduction in embedded core-based digital systems of integrated circuits (ICs) with multiple power domains
#20Semiconductor device and scan test method including writing and reading test data
#21TAP and gating enable, CaptureDR, capture, and gated CaptureDR signals
#22Tap dual port router with update lead and gated updatedr
#23Method for testing through silicon vias in 3D integrated circuits
#24Sleek serial interface for a wrapper boundary register (device and method)
#25Gating tap register control bus and auxiliary/wrapper test bus
#26Tap dual port router circuitry with gated shiftDR and clockDR
#27Core wrappers, I/O circuitry, link instruction register with and gate
#28TAP gated updateDR output AUX test control of WSP update
#29Method for testing embedded systems
#30Tap dual port router circuitry with update and capture inputs
#31TAP with AUX capture input, gated capture and shiftDR outputs
#32Semiconductor device including memory circuit and logic array
#33IC tap with dual port router and additional update input
#34Gating WSP update and TAP updatedr with TAP IR enable
#35Test apparatus and operating method thereof
#36Core wrapper link instruction register controls responsive to select signal
#37Gating WSP capture and TAP ShiftDR with TAP IR enable
#38Method and apparatus for testing I/O boundary scan chain for SoC's having I/O's powered off by default
#39SCAN CHAIN ACCESS IN 3D STACKED INTEGRATED CIRCUITS
#40IC TAP with dual port router and additional capture input
#41Test access architecture for TSV-based 3D stacked ICS
#42Wrapper selection circuits with selection and enable inputs
#43IR output of mode-1 and ATC enable; ATC gating of shift-1
#44Functional fabric based test wrapper for circuit testing of IP blocks
#45Functional fabric-based test controller for functional and structural test and debug
#46Wrapper cell for hierarchical system on chip testing
#47Multiplexer for tap controller and WSP controller outputs
#48Link instruction register with resynchronization register
#49Testable integrated circuit and test method therefor
#50Testing circuit and method
#51Link instruction register with instruction register, and gate and multiplexer
#52Interconnections for plural and hierarchical P1500 test wrappers
#53Wrapper leads gating TAP instruction and data registers
#54MOTHERBOARD TEST SYSTEM AND TEST METHOD THEREOF
#55Interconnections for plural and hierarchical P1500 test wrappers
#56Serial scan chain control within an integrated circuit
#57TEST STANDARD INTERFACES AND ARCHITECTURES
#58Method and apparatus for testing embedded cores
#59Integrated circuit chip with communication means enabling remote control of testing means of IP cores of the integrated circuit
#60Core wrappers with input and output linking circuitry
#61Method and system for backplane testing using generic boundary-scan units
#62Method and system for testing backplanes utilizing a boundary scan protocol
#63TAP IR control with TAP/WSP or WSP DR control
#64Hierarchical link instruction register core/embedded core wrapper enable signals
#65Wrapper instruction/data register controls from test access or wrapper ports
#66Method for testing through silicon vias in 3D integrated circuits
#67Scan wrapper circuit for integrated circuit