171874 ⎘
Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere; Testing of electronic circuits, e.g. by signal tracer; Testing of digital circuits; Functional testing; Reconfiguring for testing, e.g. LSSD, partitioning; Test of Modular systems, e.g. Wafers, MCM's Test of Multi-Chip-Moduls
BUILT IN SELF-TEST OF HETEROGENEOUS INTEGRATED RADIO FREQUENCY CHIPLETS
#2PACKAGE CIRCUIT INCLUDING HOMOGENEOUS DIES
#3SCAN ARCHITECTURE FOR INTERCONNECT TESTING IN 3D INTEGRATED CIRCUITS
#4INTEGRATED CIRCUIT DIE TEST ARCHITECTURE
#53D TAP & SCAN PORT ARCHITECTURES
#6SCAN TESTABLE THROUGH SILICON VIAS
#7Integrated circuit die test architecture
#8BUILT IN SELF-TEST OF HETEROGENEOUS INTEGRATED RADIO FREQUENCY CHIPLETS
#93D STACKED DIE TEST ARCHITECTURE
#10SCAN ARCHITECTURE FOR INTERCONNECT TESTING IN 3D INTEGRATED CIRCUITS
#11Cost-saving scheme for scan testing of 3D stack die
#123D tap and scan port architectures
#13Integrated circuit die test architecture
#143D stacked die test architecture
#153D TAP and scan port architectures
#16Automatic test pattern generation circuitry in multi power domain system on a chip
#17Scan architecture for interconnect testing in 3D integrated circuits
#18Integrated circuit including test circuit and method of manufacturing the same
#19Identifying causes of anomalies observed in an integrated circuit chip
#203D stacked die test architecture
#21Chip testing apparatus and system with sharing test interface
#22Integrated circuit die test architecture
#23Testing holders for chip unit and die package
#24Scan testable through silicon VIAs
#253D tap and scan port architectures
#26Test method of storage device implemented in multi-chip package (MCP) and method of manufacturing an MCP including the test method
#27Test system and probe device
#28Switch-Mode Based Interposer Enabling Self-Testing Of An MCM Without Known Good Die
#29Semiconductor chips including through electrodes and methods of testing the through electrodes
#303D stacked die test architecture
#31Integrated circuit die test architecture
#32Apparatus and method of monitoring chip process variation and performing dynamic adjustment for multi-chip system by pulse width
#333D tap and scan port architectures
#34Scalable infield scan coverage for multi-chip module for functional safety mission application
#35Scan testable through silicon VIAs
#36Probe card having dummy traces for testing an integrated circuit to be installed in a multichip-module
#37Testing holders for chip unit and die package
#38Semiconductor chips including through electrodes and methods of testing the through electrodes
#39Alignment testing for tiered semiconductor structure
#40SEMICONDUCTOR WAFER
#41IC first/second surfaces contact points, test control port, parallel scan
#42Scan architecture for interconnect testing in 3D integrated circuits
#43Scan testable through silicon VIAs
#443D tap and scan port architectures
#45Two die sides with PTI. PTO. TDI, TCK, TMS, TDO, PTIO contact points method
#46Semiconductor device and memory module including the semiconductor device
#473D chip testing through micro-C4 interface
#48Up control, CSU circuit, scan circuit, up signal contact point
#49Tap Dual Port Router, First, Second Multiplexer, First, Second Gating
#50Testing monolithic three dimensional integrated circuits
#51Scalable infield scan coverage for multi-chip module for functional safety mission application
#523D tap and scan port architectures
#53System, apparatus and method for inter-die functional testing of an integrated circuit
#54Alignment testing for tiered semiconductor structure
#55Testing holders for chip unit and die package
#56Efficient test architecture for multi-die chips
#57Stack die gating having test control input, output, and enable
#58Three state buffer, another buffer coupled to ends of tsv
#593D tap and scan port architectures
#60DYNAMICALLY CONTROLLING VOLTAGE PROVIDED TO THREE-DIMENSIONAL (3D) INTEGRATED CIRCUITS (ICs) (3DICs) TO ACCOUNT FOR PROCESS VARIATIONS MEASURED ACROSS INTERCONNECTED IC TIERS OF 3DICs
#61Systems and methods for wafer-level loopback test
#62Configurable Vertical Integration
#63Inspection circuit, semiconductor storage element, semiconductor device, and connection inspection method
#64Scan data control apparatus and electronic system having the same
#65Scan cell coupled to via ends, buffer coupled to via
#66Memory device including error detection circuit
#67Configurable Vertical Integration
#68Scan architecture for interconnect testing in 3D integrated circuits
#693D chip testing through micro-C4 interface
#70Tap dual port router with update lead and gated updatedr
#71Test circuit for 3D semiconductor device and method for testing thereof
#72Die top, bottom parallel/serial date with test and scan circuitry
#73Method for testing through silicon vias in 3D integrated circuits
#74Alignment testing for tiered semiconductor structure
#75Testing holders for chip unit and die package
#76Boundary scan chain for stacked memory
#77Interface board, a multichip package (MCP) test system including the interface board, and an MCP test method using the MCP test system
#78Through silicon via, scan cell stimulus, response to two switches
#79Multi-chip package, system and test method thereof
#80Interleaver ic with up control and capture, shift, update circuitry
#81Electrical component testing in stacked semiconductor arrangement
#82Tap dual port router circuitry with gated shiftDR and clockDR
#83Testing holders for chip unit and die package
#84Tap, test, CSU, scan circuitry with top and bottom contacts
#85SEMICONDUCTOR APPARATUS AND TEST METHOD THEREOF
#86Through-silicon via (TSV) crack sensors for detecting TSV cracks in three-dimensional (3D) integrated circuits (ICs) (3DICs), and related methods and systems
#87Electrostatic protection circuit and semiconductor device including the same
#883D integrated circuit
#89IC die with tap lock, test, scan, and up circuitry
#90Test circuit and method of controlling test circuit
#91Test circuit and method for controlling test circuit
#92Semiconductor device and method of testing semiconductor device
#93Circuit and method for monolithic stacked integrated circuit testing
#94Tap dual port router circuitry with update and capture inputs
#95Semiconductor device and method for testing the same
#96IC die test, scan, and capture, shift, and update circuitry
#97Through-substrate via (TSV) testing
#98Systems and methods for wafer-level loopback test
#99Test circuit and semiconductor apparatus including the same
#100Semiconductor apparatus and test method thereof
#101Circuit and method for monolithic stacked integrated circuit testing
#102IC die top, bottom signals, tap lock, test, scan circuitry
#103Semiconductor device for verifying operation of through silicon vias
#104Apparatus for testing a package-on-package semiconductor device
#105Test circuit and semiconductor apparatus including the same
#1063D chip testing through micro-C4 interface
#107Integrated fan-out package-on-package testing
#108Apparatus of three-dimensional integrated-circuit chip using fault-tolerant test through-silicon-via
#109Semiconductor chip, stack chip including the same, and testing method thereof
#110Electrical component testing in stacked semiconductor arrangement
#111Configurable vertical integration
#112System and method for functional verification of multi-die 3D ICs
#113Test circuit and method of semiconductor integrated circuit
#114Methodology for testing integrated circuits
#115Structure and method for testing stacked CMOS structure
#116Alignment testing for tiered semiconductor structure
#117Electrostatic discharge protection for modular equipment
#118IC tap with dual port router and additional update input
#119Circuit and method for monolithic stacked integrated circuit testing
#120Circuit and method for monolithic stacked integrated circuit testing
#121Method for scan testing three-dimensional chip
#122Semiconductor integrated circuit
#123Semiconductor device and operating method of semiconductor device
#124Semiconductor device
#125Method for testing a multi-chip system or a single chip and system thereof
#126Method for testing a plurality of transistors in a target chip
#127Test circuit and method for semiconductor device
#128Configurable vertical integration
#129Method and apparatus of wafer testing
#130Testing holders for chip unit and die package
#131Test architecture for characterizing interconnects in stacked designs
#132Scan-based test architecture for interconnects in stacked designs
#1333D built-in self-test scheme for 3D assembly defect detection
#134Detecting TSV defects in 3D packaging
#135Circuits for self-reconfiguration or intrinsic functional changes of chips before vs. after stacking
#136Boundary scan chain for stacked memory
#137Scan test of die logic in 3D ICs using TSV probing
#138Transition delay detector for interconnect test
#139Stacked chip module with integrated circuit chips having integratable built-in self-maintenance blocks
#140IC scan and test circuitry with up control circuitry
#141On-die logic analyzer for semiconductor die
#142Semiconductor apparatus and test method thereof
#143System and method for testing stacked dies
#144Configurable vertical integration
#145Test circuit and semiconductor apparatus including the same
#146Through-substrate via (TSV) testing
#147Scan, test, and control circuits coupled to IC surfaces contacts
#148Semiconductor integrated circuit with testing and repairing via
#149TEST CONTROLLER FOR 3D STACKED INTEGRATED CIRCUITS
#150Switched capacitor comparator circuit
#151System and method for functional verification of multi-die 3D ICs
#152SCAN CHAIN ACCESS IN 3D STACKED INTEGRATED CIRCUITS
#153Boundary scan chain for stacked memory
#154Methods and apparatus for testing multiple-IC devices
#155Three-dimensional integrated circuit and testing method for the same
#156SEMICONDUCTOR SYSTEM INCLUDING DATA OUTPUT CIRCUIT
#157Testing and repairing apparatus of through silicon via in stacked-chip
#158Methods and apparatus for testing multiple-IC devices
#159Method for testing multi-chip stacked packages
#160On-die logic analyzer for semiconductor die
#161METHOD OF INSPECTING AND MANUFACTURING A STACK CHIP PACKAGE
#162Programming the behavior of individual chips or strata in a 3D stack of integrated circuits
#163Programming the behavior of individual chips or strata in a 3D stack of integrated circuits
#164METHOD OF TESTING STACKED SEMICONDUCTOR DEVICE STRUCTURE
#165IC TAP with dual port router and additional capture input
#166TESTING STACKED DIE
#167Test access architecture for TSV-based 3D stacked ICS
#168Test circuit for testing through-silicon-vias in 3D integrated circuits
#169Electrostatic discharge protection for modular equipment
#170Method and apparatus for 3D IC test
#171Semiconductor device, and test method for same
#172TEST CIRCUIT AND METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT
#173SEMICONDUCTOR DEVICE INCLUDING PLURAL CORE CHIPS AND INTERFACE CHIP THAT CONTROLS THE CORE CHIPS AND CONTROL METHOD THEREOF
#174Power compensation in 3DIC testing
#175Semiconductor device, and inspection method thereof
#176METHOD OF TESTING AN OBJECT AND APPARATUS FOR PERFORMING THE SAME
#177TEST APPARATUS FOR MULTI-CHIP PACKAGE AND TEST METHOD THEREOF
#178SEMICONDUCTOR DEVICE HAVING STACKED STRUCTURE INCLUDING THROUGH-SILICON-VIAS AND METHOD OF TESTING THE SAME
#179Semiconductor apparatus and test method thereof
#180Testing die-to-die bonding and rework
#181Semiconductor device
#182Semiconductor apparatus and repairing method thereof
#183Semiconductor integrated circuit having a chip-on-chip structure
#184Semiconductor integrated circuit
#185SEMICONDUCTOR INTEGRATED CIRCUIT
#186Data channel test apparatus and method thereof
#187Method and device for measuring inter-chip signals
#188Method and device for testing TSVS in a 3D chip stack
#189CIRCUIT AND METHOD FOR TESTING SEMICONDUCTOR APPARATUS
#190Stacked semiconductor device and method of connection test in the same
#191On-die logic analyzer for semiconductor die
#192TEST ACCESS CONTROL APPARATUS AND METHOD THEREOF
#193Method and apparatus for providing through silicon via (TSV) redundancy
#194Signal repowering chip for 3-dimensional integrated circuit
#195Method, system and computer-readable code to test flash memory
#196Circuit for detecting tier-to-tier couplings in stacked integrated circuit devices
#197AUTOMATED TEST SYSTEM AND METHOD
#198Integrated tester chip using die packaging technologies
#199MULTI-CHIP PACKAGE FOR REDUCING TEST TIME
#200Data channel test apparatus and method thereof
#201Multi-chip package semiconductor device and method of detecting a failure thereof
#202Separate testing of continuity between an internal terminal in each chip and an external terminal in a stacked semiconductor device
#203Semiconductor device
#204Test circuit capable of sequentially performing boundary scan test and test method thereof
#205Method of manufacturing a system in package
#206Data channel test apparatus and method thereof
#207Device and method for testing integrated circuit dice in an integrated circuit module
#208Apparatus for non-conductively interconnecting integrated circuits
#209System-in-package and method of testing thereof
#210Stacked semiconductor device and method of testing the same
#211Semiconductor device and semiconductor device module
#212Semiconductor device and its test method
#213System and method for testing and providing an integrated circuit having multiple modules or submodules
#214Structures for semiconductor structures with error detection and correction
#215System and method for system-on-chip interconnect verification
#216Design-for-test micro probe
#217Method to improve isolation of an open net fault in an interposer mounted module
#218Test system to test multi-chip package compensating a signal distortion
#219Method and apparatus for testing embedded cores
#220Electronic device having an interface supported testing mode
#221Semiconductor device, semiconductor integrated circuit and bump resistance measurement method
#222Memory module packaging test system
#223Electronic package and method for testing the same
#224Multiple chip package test program and programming architecture
#225Memory-module manufacturing method with memory-chip burn-in and full functional testing delayed until module burn-in
#226Error detection and correction in semiconductor structures
#227Semiconductor device, and inspection method thereof
#228Multi-module simultaneous program, erase test, and performance method for flash memory
#229Multi-chip package semiconductor device and method of detecting a failure thereof
#230Electronic device having an interface supported testing mode
#231Device and method for testing integrated circuit dice in an integrated circuit module
#232System and method for system-on-chip interconnect verification
#233System and method for testing devices utilizing capacitively coupled signaling
#234System and method for testing devices utilizing capacitively coupled signaling
#235System and method for testing devices utilizing capacitively coupled signaling
#236System and method for testing devices utilizing capacitively coupled signaling
#237Shared bond pad for testing a memory within a packaged semiconductor device
#238Multi-chip package for reducing test time
#239LSI, test pattern generating method for scan path test, LSI inspecting method, and multichip module
#240Multichip package test
#241System and method for testing devices utilizing capacitively coupled signaling
#242Semiconductor device, semiconductor package, and method for testing semiconductor device
#243System-in-package and method of testing thereof
#244Semiconductor device and its test method
#245Multi-chip module and method for testing
#246System and method for testing devices utilizing capacitively coupled signaling
#247Fault tolerant semiconductor system
#248Method and apparatus for non-conductively interconnecting integrated circuits
#249Built in self-test of heterogeneous integrated radio frequency chiplets
#250Built in self-test of heterogeneous integrated radio frequency chiplets
#251System and method for schedule-based I/O multiplexing for integrated circuit (IC) scan test
#252Method for testing through silicon vias in 3D integrated circuits
#253Power distribution network IP block
#254Configuration and testing of multiple-die integrated circuits