SYSTEM AND METHOD FOR DESIGNING CLOCK MANAGEMENT UNIT USING A NO-CODE APPROACH

SECURE BUILT-IN SELF-TEST (BIST)

LOW PIN COUNT SCAN WITH NO DEDICATED SCAN ENABLE PIN

HIGH-THROUGHPUT SCAN ARCHITECTURE

Wrapper Cell Design and Built-In Self-Test Architecture for 3DIC Test and Diagnosis

METHODS AND APPARATUS TO IDENTIFY FAULTS IN PROCESSORS

X-Masking for In-System Deterministic Test

PROGRAMMABLE TEST COMPRESSION ARCHITECTURE INPUT/OUTPUT SHIFT REGISTER

TEST COMPRESSION IN A JTAG DAISY-CHAIN ENVIRONMENT

SINGLE "A" LATCH WITH AN ARRAY OF "B" LATCHES

ELECTRONIC DEVICE AND METHOD OF TESTING ELECTRONIC DEVICE

Processing Devices for reducing scan traffic, Method and Computer Program

Dynamic voltage frequency scaling to reduce test time

SYSTEMS AND METHODS TO DETECT CELL-INTERNAL DEFECTS

INTEGRATED CIRCUIT PACKAGE FOR SCAN TESTING SEMICONDUCTOR CHIP, OPERATING METHOD OF INTEGRATED CIRCUIT PACKAGE, AND INTEGRATED CIRCUIT

PROVIDING CONFIGURABLE SECURITY FOR INTELLECTUAL PROPERTY CIRCUITS OF A PROCESSOR

Hybrid solver for integrated circuit diagnostics and testing

Using scan chains to read out data from integrated sensors during scan tests

Wrapper cell design and built-in self-test architecture for 3DIC test and diagnosis

Methods and apparatus to identify faults in processors

Memory tester and test method that uses memory tester

Test compression in a JTAG daisy-chain environment

Programmable scan chain debug technique

Compressed scan chain diagnosis by internal chain observation, processes, circuits, devices and systems

Programmable test compression architecture input/output shift register coupled to SCI/SCO/PCO

Stacked Integrated Circuit Device

Single “A” latch with an array of “B” latches

Generating multiple pseudo static control signals using on-chip JTAG state machine

Scan test control decoder with storage elements for use within integrated circuit (IC) devices having limited test interface

Test architecture for electronic circuits, corresponding device and method

Universal compactor architecture for testing circuits

Interface system for interconnected die and MPU and communication method thereof

Systems and methods to detect cell-internal defects

Diagnostic enhancement for multiple instances of identical structures

Method and circuit for scan dump of latch array

Method and circuit for row scannable latch array

Programmable test compression architecture input/output shift register coupled to SCI/SCO/PCO

Suspect resolution for scan chain defect diagnosis

Systems and methods to detect cell-internal defects

Compressed scan chain diagnosis by internal chain observation, processes, circuits, devices and systems

Test compression in a JTAG daisy-chain environment

Empirical LBIST latch switching and state probability determination

System-on-chip for AT-SPEED test of logic circuit and operating method thereof

Trajectory-optimized test pattern generation for built-in self-test

Programmable scan compression

Semiconductor integrated circuit with self testing and method of testing

Programmable test compression architecture input/output shift register coupled to SCI/SCO/PCO

Scan test control decoder with storage elements for use within integrated circuit (IC) devices having limited test interface

Flexible isometric decompressor architecture for test compression

Maximization of side-channel sensitivity for trojan detection

Test circuit for dynamic checking for faults on functional and BIST clock paths to memory in both ATPG and LBIST modes

Generating multiple pseudo static control signals using on-chip JTAG state machine

Programmable test compression architecture input/output shift register coupled to SCI/SCO/PCO

System-on-chip for at-speed test of logic circuit and operating method thereof

Test compression in a JTAG daisy-chain environment

Functional circuitry, decompressor circuitry, scan circuitry, masking circuitry, qualification circuitry

Chain testing and diagnosis using two-dimensional scan architecture

DESIGN METHOD FOR SCAN TEST CIRCUIT, DESIGN PROGRAM FOR SCAN TEST CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT

Compressed test patterns for a field programmable gate array

Programmable scan compression

Memory loopback systems and methods

Software defined LFSR for LOC delay testing low-power test compression

Test generation using testability-based guidance

Isometric control data generation for test compression

Input data compression for machine learning-based chain diagnosis

TCK to shift register and decompressor on shift-DR and pause-DR

Scan chain operations

First tap, test compression architecture; second tap, test compression architecture

Multiple input signature register analysis for digital circuitry

Memory loopback systems and methods

Test response compaction scheme

Generating multiple pseudo static control signals using on-chip JTAG state machine

Logic built in self test circuitry for use in an integrated circuit with scan chains

Semiconductor integrated circuit and test method thereof

Test application time reduction using capture-per-cycle test points

In-field self-test controller for safety critical automotive use cases

Test compression in a JTAG daisy-chain environment

Compressed scan chains with three input mask gates and registers

Tap, decoder providing SC and SE to scan path circuits

Decompressed/compressed data parallel scan paths with input/output shift register, SCI/SCO

Multi-stage test response compactors

SELECTIVE PER-CYCLE MASKING OF SCAN CHAINS FOR SYSTEM LEVEL TEST

Methods and apparatus for test insertion points

Scan chain circuit supporting logic self test pattern injection during run time

Software-based self-test and diagnosis using on-chip memory

Software-based self-test and diagnosis using on-chip memory

Decompressed/compressed data parallel scan paths with tap decoded shift/scan clocks

Semiconductor device and scan test method including writing and reading test data

Integrated circuit automatic test system and integrated circuit automatic test method storing test data in scan chains

DDR TMS/TDI, addressable tap, state machine, and tap state monitor

Continuous application and decompression of test patterns and selective compaction of test responses

Semiconductor device, electronic device, and self-diagnosis method for semiconductor device

Semiconductor device, electronic control system and method for evaluating electronic control system

Logic built in self test circuitry for use in an integrated circuit with scan chains

Logic built in self test circuitry for use in an integrated circuit with scan chains

Logic built in self test circuitry for use in an integrated circuit with scan chains

Power-aware dynamic encoding

Scan compression architecture for highly compressed designs and associated methods

Scheme for masking output of scan chains in test circuit

On-chip test pattern generation

LBIST debug controller

TDI/TMS DDR coupled JTAG domain with 6 preset flip flops

Semiconductor integrated circuit and test method thereof

TDI, SC, and SE gating circuitry with count complete input

Selective per-cycle masking of scan chains for system level test

Method and apparatus for generating featured test pattern

Test apparatus for generating reference scan chain test data and test system

Multi-stage test response compactors

IC and process shifting compressed data and loading scan paths

Tap controller state machine scanning capturing plurality of scan paths

Testing a feedback shift-register

Semiconductor device, electronic device, and self-diagnosis method for semiconductor device

Method and system for digital circuit scan testing

Decompressed/compressed data parallel scan paths with input/output shift register, SCI/SCO

Test-per-clock based on dynamically-partitioned reconfigurable scan chains

Deterministic built-in self-test based on compressed test patterns stored on chip and their derivatives

Integrated circuit wafer having plural dies with each die including test circuit receiving expected data and mask data from different pads

Compressed scan chains with three input mask gates and registers

Logic-built-in-self-test diagnostic method for root cause identification

Logic-built-in-self-test diagnostic method for root cause identification

Scan test multiplexing

Scan test multiplexing

Continuous application and decompression of test patterns and selective compaction of test responses

Double data rate addressable tap interface with shadow protocol circuitry

At-speed test of memory arrays using scan

Low power testing based on dynamic grouping of scan

Scan compression architecture for highly compressed designs and associated methods

Software-based self-test and diagnosis using on-chip memory

Integrated circuit wafer having integrated circuit die with plural comparators receiving expected data and mask data from different pads

Decompressed scan chain masking circuit shift register with log2(n/n) cells

Test scheduling and test access in test compression environment

Integrated circuit and method for establishing scan test architecture in integrated circuit

Isometric test compression with low toggling activity

Method and apparatus for generating featured scan pattern

Chip authentication using scan chains

Circuit arrangement for logic built-in self-test of a semiconductor device and a method of operating such circuit arrangement

System and method for scan-testing of idle functional units in operating systems

Handling slower scan outputs at optimal frequency

Programmable access test compression architecture input and output shift registers

On-chip comparison and response collection tools and techniques

Dynamic shift for test pattern compression

Implementing MISR compression methods for test time reduction

Linear decompressor with two-step dynamic encoding

Packet based integrated circuit testing

DDR addressable TAP interface with shadow protocol and TAP domain

Power supply monitor for detecting faults during scan testing

Handling of undesirable distribution of unknown values in testing of circuit using automated test equipment

Integrated circuit with plural comparators receiving expected data and mask data from different pads

Scan chain masking qualification circuit shift register and bit-field decoders

Scheme for masking output of scan chains in test circuit

Scan chain stitching for test-per-clock

Test-per-clock based on dynamically-partitioned reconfigurable scan chains

Logic built-in self-test with high test coverage and low switching activity

Integrated circuit with toggle suppression logic

Sensor enhancement through algorithmic acquisition using synchronization with a scan generator

Scheme for masking output of scan chains in test circuit

Scan compression ratio based on fault density

Hierarchical testing architecture using core circuit with pseudo-interfaces

System and method for optimized board test and configuration

Reordering or removal of test patterns for detecting faults in integrated circuit

Two-level compression through selective reseeding

Test control point insertion and X-bounding for logic built-in self-test (LBIST) using observation circuitry

Built-in-self-test (BIST) test time reduction

Selective per-cycle masking of scan chains for system level test

IC with comparator receiving expected and mask data from pads

Delay testing capturing second response to first response as stimulus

Augmented power-aware decompressor

TCA with scan paths, decompressor, compressor, and output shift register

Signature compression register instability isolation and stable signature mask generation for testing VLSI chips

Continuous application and decompression of test patterns and selective compaction of test responses

Test data volume reduction based on test cube properties

Removing scan channel limitation on semiconductor devices

Tap with test compression architecture and start bit detector circuit

On-chip comparison and response collection tools and techniques

DDR JTAG interface setting flip-flops in high state at power-up

Increasing PRPG-based compression by delayed justification

Fault detection system, acquisition apparatus, fault detection method, program, and non-transitory computer-readable medium

Chip authentication using scan chains

High performance compaction for test responses with many unknowns

Secure low pin count scan

Scan compression architecture with bypassable scan chains for low test mode power

Iimplementing enhanced aperture function calibration for logic built in self test (LBIST)

Packetizing JTAG across industry standard interfaces

Gating of clock-DR and pause-DR from TAP to TCA

Circuit structure of test-key and test method thereof

First, update, and second TDI and TMS flip-flop TAP circuitry

IC dies with serarate connections to expected and mask data

Semiconductor integrated circuit and method of retrieving signal to semiconductor integrated circuit

Hybrid test compression architecture using multiple codecs for low pin count and high compression devices

Architecture, system, method, and computer-accessible medium for toggle-based masking

Method and apparatus for low-pin-count scan compression

System and method for debugging scan chains

synthesizing circular decompressors

Method and apparatus for fault injection

Semiconductor device and test system for testing the same

Architecture, system, method, and computer-accessible medium for partial-scan testing

Selective per-cycle masking of scan chains for system level test

Memory coupling scan input to first of scan path segments

Programmable test compression architecture with serial input register and multiplexer

IR gating SC signals during TAP Clock-DR and Pause-DR states

Structures and control processes for efficient generation of different test clocking sequences, controls and other test signals in scan designs with multiple partitions, and devices, systems and processes of making

HIGH SPEED DOUBLE DATA RATE JTAG INTERFACE

Decompressors for low power decompression of test patterns

Masking circuit removing unknown bit from cell in scan chain

Capturing response after simultaneously inputting last stimulus bit in scan path subdivisions

Integrated circuit for compression mode scan test

Data processing apparatus and method for testing a circuit block using scan chains

Fully X-tolerant, very high scan compression scan test systems and techniques

Method and apparatus for low-pin-count scan compression

Test architecture including cyclical cache chains, selective bypass scan chain segments, and blocking circuitry

Increasing PRPG-based compression by delayed justification

On-chip comparison and response collection tools and techniques

Continuous application and decompression of test patterns and selective compaction of test responses

GENERATION DEVICE, CLASSIFICATION METHOD, GENERATION METHOD, AND PROGRAM

Performance of signature-based diagnosis for logic BIST

SYSTEM FOR BOUNDARY SCAN REGISTER CHAIN COMPRESSION

Scan based test architecture and method

DECOMPRESSOR/PRPG FOR APPLYING PSEUDO-RANDOM AND DETERMINISTIC TEST PATTERNS

Generating device, generating method, and program

Method and apparatus for selectively compacting test responses

Method and apparatus for synthesis of augmented multimode compactors

DDR circuit with addressable TAP linking circuitry and plural TAPS

Method and apparatus for low-pin-count scan compression

Comparator receiving expected and mask data from circuit pads

Timing Failure Debug

Method of manufacturing a semiconductor device and a testing method of the same

Tap control of TCA scan clock and scan enable

Serial compressed data I/O in a parallel test compression architecture

Scan test application through high-speed serial input/outputs

Compactor independent direct diagnosis of test hardware

On-chip logic to support compressed X-masking for BIST

SEMICONDUCTOR INTEGRATED CIRCUIT, INFORMATION PROCESSING APPARATUS AND METHOD, AND PROGRAM

Method and system for scan chain diagnosis

Test pattern generating method, device, and program

At-speed scan testing with controlled switching activity

Compression based on deterministic vector clustering of incompatible test cubes

Circuit and method for increasing scan cell observability of response compactors

Input/output compression and pin reduction in an integrated circuit

High speed double data rate JTAG interface

Implementing hierarchical design-for-test logic for modular circuit design

Scan chain fail diagnostics

Test pattern compression

Decompressors for low power decompression of test patterns

Systems and methods for locating defective components of a circuit

Fully X-tolerant, very high scan compression scan test systems and techniques

Implementing diagnosis of transitional scan chain defects using logic built in self test LBIST test patterns

Matrix system and method for debugging scan structure

IC with comparator receiving expected and mask data from pads

Device and method for testing a circuit

Increasing scan compression by using X-chains

Phase shifter with reduced linear dependency

Test compaction using linear-matrix driven scan chains

Generating responses to patterns stimulating an electronic circuit with timing exception paths

Semiconductor device testing

Selective per-cycle masking of scan chains for system level test

Test pattern compression for an integrated circuit test environment

Test vector generating method and test vector generating program of semiconductor logic circuit device

Accurately identifying failing scan bits in compression environments

Magnetic proximity sensor system and associated methods of sensing a magnetic field

Fault diagnosis of compressed test responses

Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit

METHOD FOR PERFORMING LOGIC BUILT-IN-SELF-TEST CYCLES ON A SEMICONDUCTOR CHIP AND A CORRESPONDING SEMICONDUCTOR CHIP WITH A TEST ENGINE

Method and apparatus for selectively compacting test responses

Method for blocking unknown values in output response of scan test patterns for testing circuits

Phase shifter with reduced linear dependency

Common test logic for multiple operation modes

Continuous application and decompression of test patterns to a circuit-under-test

Decompressor/PRPG for applying pseudo-random and deterministic test patterns

Distributed test compression for integrated circuits

Testing a circuit with compressed scan chain subsets

IC with comparator receiving expected and mask data from pads

Hierarchical test response compaction for a plurality of logic blocks

Method and apparatus for synthesis of augmented multimode compactors

Method and apparatus for synthesis of augmented multimode compactors

Test method and test program of semiconductor logic circuit device

Systems and Methods for Scan Chain Testing Using Analog Signals

Method using non-linear compression to generate a set of test vectors for use in scan testing an integrated circuit

Segmented scan paths with cache bit memory inputs

Semiconductor device, a method of manufacturing a semiconductor device and a testing method of the same

Removing the effects of unknown test values from compacted test responses

Method and apparatus for broadcasting test patterns in a scan-based integrated circuit

System and Method for Nonlinear Statistical Encoding in Test Data Compression

Electrical diagnostic circuit and method for the testing and/or the diagnostic analysis of an integrated circuit

Pipeline of additional storage elements to shift input/output data of combinational scan compression circuit

Failure diagnostic apparatus, failure diagnostic system, and failure diagnostic method

Scan string segmentation for digital test compression

Methods and apparatus for communicating with a target circuit

Re-using production test scan paths for system test of an integrated circuit

Built-in self-test of integrated circuits using selectable weighting of test patterns

Conversion device, conversion method, program, and recording medium

Testing of integrated circuits using boundary scan

Input/output compression and pin reduction in an integrated circuit

Using constrained scan cells to test integrated circuits

Method and apparatus for identifying redundant scan elements

Test Point Insertion and Scan Chain Reordering for Broadcast-Scan Based Compression

System and method for self-test of integrated circuits

System and method for device performance characterization in physical and logical domains with AC SCAN testing

IC with comparator receiving expected and mask data from pads

Process for improving design limited yield by efficiently capturing and storing production test data for analysis using checksums, hash values, or digital fault signatures

Semiconductor IC and testing method thereof