171891 ⎘
Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere; Testing of electronic circuits, e.g. by signal tracer; Testing of digital circuits; Functional testing; Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG; Addressing or selecting of subparts of the device under test Identification of the subpart
METHOD AND APPARATUS TO DETECT COMPUTING SYSTEM HARDWARE DEFECTS USING A PORTABLE STORAGE DEVICE
#2INTERFACE/UNICAST FOR TEST CONTENT, FIRMWARE, AND SOFTWARE DELIVERY
#3FLEXIBLE INTERFACE
#4Circuit and method for diagnosing scan chain failures
#5Testing multi-core integrated circuit with parallel scan test data inputs and outputs
#6Test apparatus for generating reference scan chain test data and test system
#7Circuit and method for diagnosing scan chain failures
#8Error detection in stored data values
#9Tap linking module test access port controller with enable input
#10Tap controller having TMS, TCK, enable inputs and control outputs
#11Circuit and method for diagnosing scan chain failures
#12Integrated defect detection and location systems and methods in semiconductor chip devices
#13Verifying and detecting boundary scan cells to input/output mapping
#14Heterogeneous multi-core integrated circuit and method for debugging same
#15Circuit and method for diagnosing scan chain failures
#16Functional fabric based test wrapper for circuit testing of IP blocks
#17Taps and hierarchical TLM with shift register, and state machine
#18Semiconductor device having input/output wrappers, and a method of controlling the wrappers
#19HTMLS with first and second select outputs and enable inputs
#20Tap demultiplexer with select and select one outputs for HTML
#21Test device and method for hierarchical test architecture
#22Multicore chip test
#23JTAG boundary scan compliant testing architecture with full and partial disable
#24Separate scan cell in series with TAP instruction register
#25Tap with separate scan cell in series with instruction register