171894 ⎘
Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere; Testing of electronic circuits, e.g. by signal tracer; Testing of digital circuits; Functional testing; Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG Error indication, logging circuits
I3C ERROR STATES TEST STRATEGY
#2MONITOR BLOCK, INTERFACE CIRCUIT, AND METHOD OF OPERATING DEBUGGING SYSTEM
#3METHOD AND SYSTEM FOR TRACKING AND MANAGING ACTIVITIES OF TESTBENCH COMPONENTS IN A TEST ENVIRONMENT
#4Using scan chains to read out data from integrated sensors during scan tests
#5MANAGING DATA PROTECTION SETTINGS FOR AN ELECTRONIC CONTROL UNIT
#6METHOD AND APPARATUS OF ANALYZING DATA, AND STORAGE MEDIUM
#7Boundary scan test method and storage medium
#8Signal path monitor
#9Single-pass diagnosis for multiple chain defects
#10Error rate measuring apparatus and data division display method
#11System-on-chip for AT-SPEED test of logic circuit and operating method thereof
#12Optimized scan chain diagnostic pattern generation for reversible scan architecture
#13System-on-chip for at-speed test of logic circuit and operating method thereof
#14Method for identifying a fault at a device output and system therefor
#15Integrated circuit fault detection
#16Semiconductor device, electronic device, and self-diagnosis method for semiconductor device
#17Built-in device testing of integrated circuits
#18Method, device and article to test digital circuits
#19Debugging method executed via scan chain for scan test and related circuitry system
#20Test apparatus for generating reference scan chain test data and test system
#21Semiconductor device, electronic device, and self-diagnosis method for semiconductor device
#22Scan test multiplexing
#23Scan test multiplexing
#24Generating test sets for diagnosing scan chain failures
#25Localizing fault flop in circuit by using modified test pattern
#26Isolating failing latches using a logic built-in self-test
#27Scan chain fault diagnosis
#28Integrated circuits capable of generating test mode control signals for scan tests
#29Methods and systems for logic device defect tolerant redundancy
#30Digital integrated circuit testing and characterization system and method
#31Scan chain fault diagnosis
#32Generating test sets for diagnosing scan chain failures
#33Profiling-based scan chain diagnosis
#34Communication of a diagnostic signal and a functional signal by an integrated circuit
#35Enhanced diagnosis with limited failure cycles
#36TESTABLE INTEGRATED CIRCUIT AND IC TEST METHOD
#37Probeless DC testing of CMOS I/O circuits
#38Generating test sets for diagnosing scan chain failures
#39implementing deterministic based broken scan chain diagnostics
#40Communication of a diagnostic signal and a functional signal by an integrated circuit
#41Process for identifying the location of a break in a scan chain in real time
#42System and method for device performance characterization in physical and logical domains with AC SCAN testing
#43Method and apparatus for detecting and correcting soft-error upsets in latches
#44Defect localization based on defective cell diagnosis
#45Diagnosing mixed scan chain and system logic defects
#46Method to prevent firmware defects from disturbing logic clocks to improve system reliability
#47Scan testing in single-chip multicore systems
#48Enhanced diagnosis with limited failure cycles
#49Methods and apparatus for error injection
#50Probeless DC testing of CMOS I/O circuits
#51IC with protocol selection memory coupled to serial scan path
#52Semiconductor integrated circuit having test function and manufacturing method
#53Localizing error detection and recovery
#54Store scan data in trace arrays for on-board software access
#55Method and apparatus for selective scan chain diagnostics
#56Process variation detector and process variation detecting method
#57IC with expected data memory coupled to scan data register
#58Method for implementing deterministic based broken scan chain diagnostics
#59ABIST-assisted detection of scan chain defects
#60IC with protocol selection memory coupled to serial scan path
#61Highly accurate defect identification and prioritization of fault locations