POWER MANAGEMENT CLUSTER DESIGN SYSTEM AND METHOD USING A NO-CODE APPROACH

CLOCK SIGNAL CONTROL FOR SCAN-CHAIN TESTING

METHODS AND APPARATUSES FOR A MATRIX SCAN ARCHITECTURE

HIGH-THROUGHPUT SCAN ARCHITECTURE

Method of finding optimized analog measurement hardware settings as well as method of measuring a device under test

Wafer scale testing using a 2 signal JTAG interface

Automatic test pattern generation circuitry in multi power domain system on a chip

METHOD FOR TESTING POWER LEAKAGE OF CIRCUIT AND PROCESSING SYSTEM USING SAME

Power profiling in an integrated circuit having a current sensing circuit

Test access port architecture to facilitate multiple testing modes

Wafer scale testing using a 2 signal JTAG interface

Power consumption measurement assembly and method, and chip power consumption measurement device

Phase controlled codec block scan of a partitioned circuit device

Test access port architecture to facilitate multiple testing modes

Wafer scale testing using a 2 signal JTAG interface

Phase controlled codec block scan of a partitioned circuit device

Power-aware scan partitioning

Method for reducing power consumption in scannable flip-flops without additional circuitry

Built-in self-test in a data processing apparatus

Test access port architecture to facilitate multiple testing modes

Dynamically power noise adaptive automatic test pattern generation

Systems on chips, integrated circuits, and operating methods of the integrated circuits

Channel circuitry, tap linking module, scan tap, debug tap domains

Wafer with dio bidirectional lead, n dies, domains, clock leads

Method for identifying a fault at a device output and system therefor

Power-aware scan partitioning

Regulator control during scan shift and capture cycles

SYSTEM AND METHOD FOR REDUCING POWER CONSUMPTION IN SCANNABLE CIRCUIT

Wafer tap domain die channel circuitry with separate die clocks

Semiconductor integrated circuit and semiconductor integrated circuit diagnosis method

Two signal JTAG with TLM, scan domain and diagnostics domain

Integrated circuit with low power scan system

Scan circuitry with IDDQ verification

Semiconductor device, electronic device, and self-diagnosis method for semiconductor device

Solid state switch power emulator

First, second divided scan paths, adaptor, generator and compactor circuitry

Cores with separate serial scan paths and scan path parts

Integrated circuit with low power scan system

Two signal JTAG wafter testing bist and scan tap domains

IC cores, scan paths, compare circuitry, select and enable inputs

Reducing power requirements and switching during logic built-in-self-test and scan test

Selectable separate scan paths with hold state multiplexer and adapter

IC die with channel circuitry, scan and BIST taps, TLM

Low power scan path cells with hold state multiplexer circuitry

Semiconductor device, electronic device, and self-diagnosis method for semiconductor device

Semiconductor storage device having synchronous and asynchronous modes

Test-per-clock based on dynamically-partitioned reconfigurable scan chains

Mode based skew to reduce scan instantaneous voltage drop and peak currents

Wafer scale testing using a 2 signal JTAG interface

Scan test multiplexing

Scan test multiplexing

System on chip

Divided scan path cells with first and state hold multiplexers

Control test point for timing stability during scan capture

Electronic device and method for state retention

Method and control device for launch-off-shift at-speed scan testing

Method and apparatus for scan chain data management

PSD/PSC serial scan path having first and second strobe inputs

Low power testing based on dynamic grouping of scan

Low power Scan-BIST test data generator and compactor pass/fail output

Method and apparatus for at-speed scan shift frequency test optimization

Scan test system with a test interface having a clock control unit for stretching a power shift cycle

Fault detection system, generation circuit, and program

Enable and select inputs operate combinational logic parallel scan paths

Circuit arrangement for logic built-in self-test of a semiconductor device and a method of operating such circuit arrangement

Semiconductor integrated circuit and power-supply voltage adaptive control system

Coverage enhancement and power aware clock system for structural delay-fault test

Parallel scan path distributor/collector controller having serial and control inputs

Control test point for timing stability during scan capture

Packet based integrated circuit testing

System on chip for debugging a cluster regardless of power state of the cluster, method of operating the same, and system having the same

Identification of power sensitive scan cells

Power supply monitor for detecting faults during scan testing

Scan chain stitching for test-per-clock

Test-per-clock based on dynamically-partitioned reconfigurable scan chains

Logic built-in self-test with high test coverage and low switching activity

Wired-or fail flag in serial stimulus, expected/mask data test circuitry

Automatable scan partitioning for low power using external control

Integrated circuit testing with power collapsed

System for reducing peak power during scan shift at the global level for scan based tests

Global low power capture scheme for cores

High density low power scan flip-flop

Delay testing capturing second response to first response as stimulus

Core circuit test architecture

Translating operate state into operate scan paths, A, B, C

Synchronizer and buffers delaying strobe to individual parallel scan paths

Controlled toggle rate of non-test signals during modular scan testing of an integrated circuit

State machine shifting between idle, capture, shift 1, shift 2

Operating scan path generators and compactors sequentially and capturing simultaneously

Method and apparatus for testing I/O boundary scan chain for SoC's having I/O's powered off by default

Low leakage boundary scan device design and implementation

POWER DROOP REDUCTION VIA CLOCK-GATING FOR AT-SPEED SCAN TESTING

Scan chain modification for reduced leakage

Integrated circuit leakage power reduction using enhanced gated-Q scan techniques

System for testing electronic circuits

Reducing power consumption during manufacturing test of an integrated circuit

Systems, processes and computer-accessible medium for providing a bi-directional scan path for peak capture power reduction in launch-off-shift testing

Semiconductor integrated circuit including a power controllable region

Low leakage current operation of integrated circuit using scan chain

Integrated circuit with transition control circuitry for limiting scan test signal transitions during scan testing

Decode logic driving segmented scan cells with clocks and enables

State machine transitioning between idle, capture, shift-I, and shift-2 states

Tap with three multiplexers and port enable control output

Generator/compactor scan circuit low power adaptor with state machine

Test generator for low power built-in self-test

Low-power and area-efficient scan cell for integrated circuit testing

Integrated circuit testing with power collapsed

Compare circuitry with scan cell separate from serial scan circuitry

Low Power Scan-Based Testing

Memory coupling scan input to first of scan path segments

Semiconductor integrated circuit and power-supply voltage adaptive control system

Measuring power consumption in an integrated circuit

Integrated circuit leakage power reduction using enhanced gated-Q scan techniques

Scan-based reset

Scan cell use with reduced power consumption

Moving data through test control register with state machine states

Core circuit test architecture

Semiconductor integrated circuit including a power controllable region

Low leakage boundary scan device design and implementation

Capturing response after simultaneously inputting last stimulus bit in scan path subdivisions

Operating scan paths sequentially and capturing simultaneously

Shifting bits in different scan paths with steady TMS

Die with DIO path, clock input, TLM, and TAP domains

Receiving control signals and operating separate scan paths with adaptor

Sequential digital circuitry with test scan

Method of testing functioning of a semiconductor device

Divided scan path segments maintaining test pattern of stimulus/response connections

Low power scan testing techniques and apparatus

Scan architecture and design methodology yielding significant reduction in scan area and power overhead

Adapting scan-BIST architectures for low power operation

Adaptor With Clocks For Like Parts of Different Scan Paths

IC with TAP, DIO interface, SIPE, and PISO circuits

Method and system thereof for optimization of power consumption of scan chains of an integrated circuit for test

Gating circuitry coupling selected scan paths between I/O scan bus

Automatable scan partitioning for low power using external control

Dual controllers for scan paths, distributors, and collectors

Changing scan paths shifting by changing mode select input state

Semiconductor integrated circuit and method of testing the same

Wafer scale testing using a 2 signal JTAG interface

At-speed scan testing with controlled switching activity

Circuit module, semiconductor integrated circuit, and inspection apparatus and method thereof

Semiconductor integrated circuit including a power controllable region

Generator/compactor scan circuit low power adapter

Semiconductor integrated circuit and method for testing the same

Circuit and method providing dynamic scan chain partitioning

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR TESTING METHOD

Core circuit test architecture

Test generation methods for reducing power dissipation and supply currents

Low power testing of very large circuits

Scan path adaptor with state machine, counter, and gate circuitry

Automatable scan partitioning for low power using external control

Circuits and methods employing a local power block for leakage reduction

ISOLATION CELL WITH TEST MODE

Testing state retention logic in low power systems

Compressor/decompressor circuits coupled with TDO-TMS/TDI die channel circuitry

Shift-frequency scaling

Scalable scan-based test architecture with reduced test time and test power

Scan chain modification for reduced leakage

BIST scan path parts with test generator and compactor circuitry

Method of stitching scan flipflops together to form a scan chain with a reduced wire length

Method and apparatus for on-the-fly minimum power state transition

Semiconductor integrated circuit and method for testing the same

Testing embedded circuits with the aid of a separate supply voltage

MEASUREMENT OF POWER CONSUMPTION WITHIN AN INTEGRATED CIRCUIT

Analog IC having test arrangement and test method for such an IC

Adapting scan architectures for low power operation

Low power testing of very large circuits

Staggered LBIST Clock Sequence for Noise (di/dt) Amelioration

Pulse latch circuit and semiconductor integrated circuit

Circuit having a local power block for leakage reduction

Segmented scan paths with cache bit memory inputs

Testing Using Independently Controllable Voltage Islands

Wafer scale testing using a 2 signal JTAG interface

Semiconductor chip with a plurality of scannable storage elements and a method for scanning storage elements on a semiconductor chip

Power saving flip-flop

Sharing routing of a test signal with an alternative power supply to combinatorial logic for low power design

Method of testing a semiconductor integrated circuit

Method and apparatus for on-the-fly minimum power state transition

Circuitry to prevent peak power problems during scan shift

Double-edge triggered scannable pulsed flip-flop for high frequency and/or low power applications

Method and circuit for measuring operating and leakage current of individual blocks within an array of test circuit blocks

Low power scan testing techniques and apparatus

Lowering power consumption during logic built-in self-testing (LBIST) via channel suppression

CORE CIRCUIT TEST ARCHITECTURE

Optimizing a Set of LBIST Patterns to Enhance Delay Fault Coverage

Modifying a test pattern to control power supply noise

DOUBLE-EDGE TRIGGERED SCANNABLE PULSED FLIP-FLOP FOR HIGH FREQUENCY AND/OR LOW POWER APPLICATIONS

System and method for advanced logic built-in self test with selection of scan channels

Logic device and method supporting scan test

Integrated circuit with low-power built-in self-test logic

DFT techniques to reduce test time and power for SoCs

Test generation methods for reducing power dissipation and supply currents

Semiconductor integrated circuit apparatus and control method thereof

Semiconductor integrated circuit having built-n self test circuit of logic circuit and embedded device, and design apparatus thereof

Electronic circuit and integrated circuit including scan testing circuit, and power consumption reducing method used for integrated circuit

PARALLEL ARCHITECTURE FOR LOW POWER LINEAR FEEDBACK SHIFT REGISTERS

Low power scan process with connected stimulus and scan paths

Automatable scan partitioning for low power using external control

Efficient calculation of a number of transitions and estimation of power dissipation in sequential scan tests

Testing combinational logic die with bidirectional TDI-TMS/TDO chanel circuit

Separately controlled scan paths of functional registers providing stimulus/response data

Semiconductor integrated circuit device, method of testing the same, database for design of the same and method of designing the same

Method and apparatus for test connectivity, communication, and control

In-circuit testing system and method

Shift register, scanning line driving circuit, matrix type device, electro-optic device, and electronic device

Sequential scan technique for testing integrated circuits with reduced power, time and/or cost

Digital storage element with enable signal gating

Reducing Power Dissipation During Sequential Scan Tests

Redundancy power for communication devices

Digital storage element with dual behavior

Digital storage element architecture comprising integrated multiplexer and reset functionality

Scan test design method, scan test circuit, scan test circuit insertion cad program, large-scale integrated circuit and mobile digital equipment

Pulse latch circuit and semiconductor integrated circuit

Scan sequenced power-on initialization

BIST with generator, compactor, controller, adaptor, and separate scan paths

Semiconductor integrated circuit and method for testing the same

Testing using independently controllable voltage islands

Method and apparatus for controlling AC power during scan operations in scannable latches

Scan chain partition for reducing power in shift mode

Method of using scan chains and boundary scan for power saving

Test clocking scheme

High speed energy conserving scan architecture

Semiconductor integrated circuit having bonding optional function

Power-saving retention mode

Control signal generator, latch circuit, flip flop and method for controlling operations of the flip-flop

Method on scan chain reordering for lowering VLSI power consumption

Semiconductor integrated circuit having test circuitry with reduced power consumption

Response bits as stimulus in subdivided scan path delay test

IC with parallel scan paths and compare circuitry

Integrated circuit with leakage control and method for leakage control

Methods and arrangements for an enhanced scanable latch circuit

Scan chain modification for reduced leakage

Means scanning scan path parts sequentially and capturing response simultaneously

Power-sensitive scan-chain testing

Augmenting an integrated circuit (IC) design simulation model to improve performance during verification

Power saving scannable latch output driver

Low-power shift with clock staggering

2D compression-based low power ATPG