171897 ⎘
Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere; Testing of electronic circuits, e.g. by signal tracer; Testing of digital circuits; Functional testing; Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG AC testing, e.g. current testing, burn-in
Sub-classes:TESTING CIRCUIT
#2Scan testing using scan frames with embedded commands
#3SCAN TESTING USING SCAN FRAMES WITH EMBEDDED COMMANDS
#4Array of Through-Silicon Via Contact Points on a Semiconductor Die
#5Wafer scale testing using a 2 signal JTAG interface
#6TSV testing using test circuits and grounding means
#7Wafer scale testing using a 2 signal JTAG interface
#8Scan testing using scan frames with embedded commands
#9Controller structural testing with automated test vectors
#10TSV testing using test circuits and grounding means
#11Wafer scale testing using a 2 signal JTAG interface
#12Controller structural testing with automated test vectors
#13TSVS, test circuits, scan cells, comparators, electrical source, and resistor
#14IC test architecture having differential data input and output buffers
#15Channel circuitry, tap linking module, scan tap, debug tap domains
#16IC TSV scan cells with sensed and reference voltage inputs
#17Wafer with dio bidirectional lead, n dies, domains, clock leads
#18Method and system for monitoring quality and controlling an alternating current power supply provided to an ultrasound system from a power outlet
#19Input shift register having parallel serial scan outputs, command output
#20Wafer tap domain die channel circuitry with separate die clocks
#21Two signal JTAG with TLM, scan domain and diagnostics domain
#22TSV first ends connected to test stimulus and response signals
#23Scan circuitry with IDDQ verification
#24Differential I/O for parallel scan paths, scan frames, embedded commands
#25Cores with separate serial scan paths and scan path parts
#26Two signal JTAG wafter testing bist and scan tap domains
#27IC die with channel circuitry, scan and BIST taps, TLM
#28Low power scan path cells with hold state multiplexer circuitry
#29Method and apparatus for evaluating and optimizing a signaling system
#30Scan testing scan frames with embedded commands and differential signaling
#31Boundary scan testing a storage device via system management bus interface
#32Testing TSV with current/voltage source, resistor, comparator, and scan cell
#33Chip performance monitoring system and method
#34Wafer scale testing using a 2 signal JTAG interface
#35Divided scan path cells with first and state hold multiplexers
#36Gated state machine circuitry having three clock 2 enable states
#37Method and apparatus for at-speed scan shift frequency test optimization
#38Method and apparatus for evaluating and optimizing a signaling system
#39Automatable scan partitioning for low power using external control
#40Circuit and method for measuring delays between edges of signals of a circuit
#41Chip performance monitoring system and method
#42Translating operate state into operate scan paths, A, B, C
#43Scan test controller with state machine and gates
#44Scan chain modification for reduced leakage
#45TSVs connected to ground and combined stimulus and testing leads
#46System for testing electronic circuits
#47Decode logic driving segmented scan cells with clocks and enables
#48Parallel scan paths with stimulus and header data circuitry
#49Method and apparatus for evaluating and optimizing a signaling system
#50Integrated circuit devices having selectively enabled scan paths with power saving circuitry
#51Scan paths, stimulus, and header circuitry with command/frame marker outputs
#52Die with DIO path, clock input, TLM, and TAP domains
#53Receiving control signals and operating separate scan paths with adaptor
#54Method and apparatus for testing electrical connections on a printed circuit board
#55Circuit and method for simultaneously measuring multiple changes in delay
#56Divided scan path segments maintaining test pattern of stimulus/response connections
#57Adaptor With Clocks For Like Parts of Different Scan Paths
#58IC with TAP, DIO interface, SIPE, and PISO circuits
#59Automatable scan partitioning for low power using external control
#60Wafer scale testing using a 2 signal JTAG interface
#61Pseudo-Random Balanced Scan Burnin
#62Method and apparatus for evaluating and optimizing a signaling system
#63Semiconductor device test circuit, semiconductor device, and its manufacturing method
#64Speed-path debug using at-speed scan test patterns
#65SEMICONDUCTOR DEVICE AND SEMICONDUCTOR TESTING METHOD
#66Scan path adaptor with state machine, counter, and gate circuitry
#67Automatable scan partitioning for low power using external control
#68Parallel scan paths with header data circuitry and header return circuitry
#69Method for testing semiconductor integrated circuit and method for verifying design rules
#70Compressor/decompressor circuits coupled with TDO-TMS/TDI die channel circuitry
#71Scan chain modification for reduced leakage
#72Scannable virtual rail ring oscillator circuit and system for measuring variations in device characteristics
#73Adapting scan architectures for low power operation
#74Wafer scale testing using a 2 signal JTAG interface
#75SEMICONDUCTOR MEMORY DEVICE
#76Methods and apparatus for communicating with a target circuit
#77Scannable virtual rail method and ring oscillator circuit for measuring variations in device characteristics
#78Monitoring system for detecting and characterizing classes of leakage in CMOS devices
#79Scan testing using scan frames with embedded commands
#80Semiconductor integrated circuit
#81Low power scan process with connected stimulus and scan paths
#82METHOD AND APPARATUS FOR EVALUATING AND OPTIMIZING A SIGNALING SYSTEM
#83Automatable scan partitioning for low power using external control
#84Testing combinational logic die with bidirectional TDI-TMS/TDO chanel circuit
#85Method for testing semiconductor integrated circuit and method for verifying design rules
#86Method and apparatus for evaluating and optimizing a signaling system
#87Device design-for-test and burn-in-board with minimal external components and increased testing capacity
#88Method and apparatus for presetting an amplifier
#89Power reduction in module-based scan testing
#90AC testing of leakage current in integrated circuits using RC time constant
#91Method of inspecting actual speed of semiconductor integrated circuit
#92Serial burn-in monitor
#93Built in self test
#94Circuit and method for comparing circuit performance between functional and AC scan testing in an integrated circuit (IC)
#95Self-testing input/output pad
#96Signal pin tester for AC defects in integrated circuits
#97Enhanced JTAG interface
#98Simultaneous AC logic self-test of multiple clock domains
#99Mechanism to enhance observability of integrated circuit failures during burn-in tests
#100Method and apparatus for generating signal transitions used for testing an electronic device
#101Scan chain modification for reduced leakage
#102Testing a multi-channel device
#103Integrated device with an improved BIST circuit for executing a structured test
#104Semiconductor integrated circuit, and electrostatic withstand voltage test method and apparatus therefor