171901 ⎘
Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere; Testing of electronic circuits, e.g. by signal tracer; Testing of digital circuits; Functional testing; Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG; Design for test Security aspects
SECURE SCAN TESTING OF INTEGRATED CIRCUITS
#2DEBUG SYSTEM AND METHOD FOR OPERATING A DEBUG SYSTEM
#3Scan Test Security for Semiconductor Devices
#4DEBUG INFRASTRUCTURE FOR MEMORY SYSTEMS
#5Secure chip capable of generating secure data by itself
#6PROTECTION OF THE CONTENT OF A FUSE MEMORY
#7TECHNIQUES FOR INFIELD TESTING OF CRYPTOGRAPHIC CIRCUITRY
#8Secured scan access for a device including a scan chain
#9SCAN FLIP-FLOP, SCAN CHAIN CIRCUIT INCLUDING THE SAME, AND CONTROL METHOD OF THE SCAN FLIP-FLOP
#10SECURED SCAN ACCESS FOR A DEVICE INCLUDING A SCAN CHAIN
#11PROVIDING CONFIGURABLE SECURITY FOR INTELLECTUAL PROPERTY CIRCUITS OF A PROCESSOR
#12Invisible scan architecture for secure testing of digital designs
#13Reconfigurable JTAG architecture for implementation of programmable hardware security features in digital designs
#14Protection of the content of a fuse memory
#15Using embedded time-varying code generator to provide secure access to embedded content in an on-chip access architecture
#16IC device authentication using energy characterization
#17Side-channel signature based PCB authentication using JTAG architecture and a challenge-response mechanism
#18IC device authentication using energy characterization
#19Detection of pulse width tampering of signals
#20Design-for-test for asynchronous circuit elements
#21Secure device state apparatus and method and lifecycle management
#22Using embedded time-varying code generator to provide secure access to embedded content in an on chip access architecture
#23Design-for-test for asynchronous circuit elements
#24JTAG lockout for embedded processors in programmable devices
#25Device and method for detecting points of failures
#26Secure device state apparatus and method and lifecycle management
#27Test point-enhanced hardware security
#28System on chip and secure debugging method
#29Using embedded time-varying code generator to provide secure access to embedded content in an on chip access architecture
#30Electronic system, system diagnostic circuit and operation method thereof
#31Non-intrusive monitoring
#32Protecting chip settings using secured scan chains
#33Protecting hidden content in integrated circuits
#34Protecting hidden content in integrated circuits
#35Device having secure JTAG and debugging method for the same
#36Protecting information processing system secrets from debug attacks
#37Method for producing an electronic device with a disabled sensitive mode, and method for transforming such an electronic device to re-activate its sensitive mode
#38Protection of proprietary embedded instruments
#39Processor switchable between test and debug modes
#40Secure low pin count scan
#41Semiconductor device
#42Circuit for securing scan chain data
#43Protecting chip settings using secured scan chains
#44APPARATUS AND METHOD OF AUTHENTICATING JOINT TEST ACTION GROUP (JTAG)
#45Protection of proprietary embedded instruments
#46Apparatus and method of authenticating joint test action group (JTAG)
#47METHODS AND APPARATUS FOR TESTING AN IC USING A PLURALITY OF I/O LINES
#48Method and system for blocking data in scan registers from being shifted out of a device
#49Method and apparatus for transferring hidden signals in a boundary scan test interface
#50Method and apparatus for accessing hidden data in a boundary scan test interface
#51Semiconductor LSI circuit with scan circuit, scan circuit system, scanning test system and method
#52Methods and apparatus for testing an IC
#53IC device authentication using energy characterization
#54IC device authentication using energy characterization
#55Securing access to integrated circuit scan mode and data