171902 ⎘
Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere; Testing of electronic circuits, e.g. by signal tracer; Testing of digital circuits; Functional testing; Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG; Design for test Tools
ELECTRONIC DEVICE AND METHOD OF TESTING ELECTRONIC DEVICE
#2Processing Devices for reducing scan traffic, Method and Computer Program
#3Scan apparatus capable of fault diagnosis and scan chain fault diagnosis method
#4JTAG bus communication method and apparatus
#5Serial data communication modes on TDI/TDO, receive TMS, send TMS
#6DESIGN METHOD FOR SCAN TEST CIRCUIT, DESIGN PROGRAM FOR SCAN TEST CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT
#7Tap, counter storing value of serial access by communication circuitry
#8Signals on tap bi-directional TMS terminal selecting serial communication register
#9JTAG scans through packetization
#10Internal circuit TMS input, FIFO coupled to parallel-input serial-output register
#11TMS pin for mode signal and output for read data
#12TMS serial communication circuitry coupled to tap IR enable output
#13Bi-directional TCK lead carrying TCK and frame data in/out signal
#14Tap, data input, output circuitry coupled to mode select lead
#15I/O circuitry free of test clock coupled with destination/source circuitry
#16Test access port and TMS communication circuitry with state machines
#17Mechanism to instantiate a JTAG debugger in a browser
#18Bi-directional TMS lead carrying TMS and frame data in/out signals
#19Source and destination data circuitry coupled to bi-directional TMS lead
#20JTAG bus communication method and apparatus
#21EDA TOOL, SEMICONDUCTOR DEVICE, AND SCAN CHAIN CONFIGURATION METHOD
#22Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit
#23JTAG bus communication method and apparatus
#24Enhancing speed of simulation of an IC design while testing scan circuitry
#25Scheme to optimize scan chain ordering in designs
#26JTAG TEST CODE AND DATA COMPILER AND METHOD
#27Method and apparatus for broadcasting test patterns in a scan-based integrated circuit
#28Boundary scan connector test method capable of fully utilizing test I/O modules
#29Scan test circuit, semiconductor integrated circuit and scan enable signal time control circuit
#30Double-edge triggered scannable pulsed flip-flop for high frequency and/or low power applications
#31implementing deterministic based broken scan chain diagnostics
#32Chip level scan chain planning for hierarchical design flows
#33JTAG circuit transferring data between devices on TCK terminals
#34Semiconductor integrated circuit device, method of testing the same, database for design of the same and method of designing the same
#35Scan test design method, scan test circuit, scan test circuit insertion cad program, large-scale integrated circuit and mobile digital equipment
#36Method and apparatus for broadcasting test patterns in a scan based integrated circuit
#37System for performing automatic test pin assignment for a programmable device
#38Method for implementing deterministic based broken scan chain diagnostics
#39JTAG circuit transferring data between devices on TMS terminals
#40Method of grouping scan flops based on clock domains for scan testing
#41Low-power shift with clock staggering
#42Test techniques and circuitry