171911 ⎘
Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere; Testing of electronic circuits, e.g. by signal tracer; Testing of digital circuits; Functional testing; Tester hardware, i.e. output processing circuits tester configuration Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns
Sub-classes:METHOD AND SYSTEM FOR PERFORMING TRANSFER FUNCTION MEASUREMENTS ON A DEVICE
#2METHOD, SYSTEM, DEVICE, AND MEDIA RELATED TO DRIFT VERIFICATION
#3METHODS AND APPARATUS TO GENERATE SEMICONDUCTOR PRODUCT YIELD INDICATORS
#4TEST CONTROL DEVICE AND OPERATING METHOD THEREOF
#5Functional Circuit Block Harvesting in Integrated Circuits
#6PLUGGABLE LOAD MODULE TO TEST A VOLTAGE REGULATOR
#7DATA SIMULATION APPARATUS AND DATA SIMULATION METHOD
#8TESTING MULTI-CYCLE PATHS BASED ON CLOCK PATTERN
#9MULTI-USER DEVELOPMENT SYSTEM FOR SYSTEM LEVEL DEVICE TESTING
#10SYSTEM FOR TESTING AN INTEGRATED CIRCUIT OF A DEVICE AND ITS METHOD OF USE
#11SYSTEM FOR TESTING AN INTEGRATED CIRCUIT OF A DEVICE AND ITS METHOD OF USE
#12AUTOMATED TEST EQUIPMENT AND METHOD USING A TRIGGER GENERATION
#13UNIVERSAL DETECTION DEVICE AND METHOD FOR HIGH SPEED DIGITAL INTERFACE OF INTEGRATED CIRCUIT
#14MEASUREMENT INSTRUMENT, MEASUREMENT SYSTEM, AND SIGNAL PROCESSING METHOD
#15METHOD AND SYSTEM FOR TESTING BLOCKS WITHIN DEVICE UNDER TEST (DUT) USING RECONFIGURABLE TEST LOGIC
#16CONFIGURABLE PIN DRIVER CIRCUIT OUTPUT IMPEDANCE BACKGROUND
#17METHOD AND SYSTEM FOR TRACKING AND MANAGING ACTIVITIES OF TESTBENCH COMPONENTS IN A TEST ENVIRONMENT
#18SYSTEM FOR TESTING AN INTEGRATED CIRCUIT OF A DEVICE AND ITSMETHOD OF USE
#19SYSTEM FOR TESTING AN INTEGRATED CIRCUIT OF A DEVICE AND ITS METHOD OF USE
#20Random function selection and insertion during compilation for post-silicon validation
#21SYSTEM FOR TESTING AN INTEGRATED CIRCUIT OF A DEVICE AND ITS METHOD OF USE
#22SYSTEM FOR TESTING AN INTEGRATED CIRCUIT OF A DEVICE AND ITS METHOD OF USE
#23AUTOMATED TEST EQUIPMENT, DEVICE UNDER TEST, TEST SETUP METHODS USING AN ACKNOWLEDGE SIGNALING
#24OPTICAL TUNING TEST SYSTEM USING PARALLEL OVEN PIPELINES WITH PARALLEL INSTRUMENT CHANNELS AND MACHINE LEARNING ASSISTANCE
#25Controlling storage of test data based on prior test program execution
#26DEFECT EVALUATION METHOD FOR EVALUATING DEFECT DUE TO ELECTROSTATIC DISCHARGE AND DEFECT EVALUATION DEVICE PERFORMING THE SAME
#27GRPC-Based Chip Test Method, GRPC-Based Chip Test Apparatus, and Storage Medium
#28Functional Circuit Block Harvesting in Computer Systems
#29METHODS, SYSTEMS, AND COMPUTER READABLE MEDIA FOR USING A TESTBED TRANSPILER
#30Device under test simulation equipment
#31TUNING A DEVICE UNDER TEST USING PARALLEL PIPELINE MACHINE LEARNING ASSISTANCE
#32System and method of over-the-air testing of a device under test
#33DEVICES AND METHODS FOR TESTING OF FAR-FIELD WIRELESS CHARGING
#34AUTOMATED TEST EQUIPMENT AND METHOD USING A TRIGGER GENERATION
#35Systems and Methods for Measurement of a Parameter of a DUT
#36Board adapter device, test method, system, apparatus, and device, and storage medium
#37Testbenches for electronic systems with automatic insertion of verification features
#38Software-Defined Synthesizable Testbench
#39Test method and apparatus of communication chip, device and medium
#40Compiler-based code generation for post-silicon validation
#41Bit error ratio estimation using machine learning
#42SYSTEM FOR TESTING AN INTEGRATED CIRCUIT OF A DEVICE AND ITS METHOD OF USE
#43System and method of testing single DUT through multiple cores in parallel
#44Measurement system for identifying aggressor signals
#45Device under test synchronization with automated test equipment check cycle
#46Reformatting scan patterns in presence of hold type pipelines
#47Signal processing method
#48System and method for separation and classification of signals using cyclic loop images
#49SYSTEM AND METHOD FOR MULTI-LEVEL SIGNAL CYCLIC LOOP IMAGE REPRESENTATIONS FOR MEASUREMENTS AND MACHINE LEARNING
#50Cyclic loop image representation for waveform data
#51Electrical testing apparatus for spintronics devices
#52Test equipment diagnostics systems and methods
#53Vector Eyes
#54Chip test method, apparatus, device, and system
#55Trajectory-optimized test pattern generation for built-in self-test
#56Automated test equipment for testing one or more devices under test, method for automated testing of one or more devices under test, and computer program for handling command errors
#57Digital circuit robustness verification method and system
#58Automated test equipment for testing one or more devices under test, method for automated testing of one or more devices under test, and computer program using a buffer memory
#59Data channel optimization with smart black box algorithms
#60Automated test equipment using an on-chip-system test controller
#61Measurement device and method of setting a measurement device
#62Method and device for sending data according to a signal timing
#63Test system supporting reverse compliance
#64Test method and test system
#65SYSTEM AND METHODS FOR DYNAMICALLY RECONFIGURING AUTOMATIC TEST EQUIPMENT
#66System for testing an integrated circuit of a device and its method of use
#67Electrical testing apparatus for spintronics devices
#68Methods and systems for testing a tester
#69System and method for temporal signal measurement of device under test (DUT) and method of forming system
#70Wafer probe card integrated with a light source facing a device under test side and method of manufacturing
#71Device and methods for reducing peak noise and peak power consumption in semiconductor devices under test
#72Method and system for acquisition of test data
#73Test equipment for over the air tests as well as method for testing a device under test
#74Smart and efficient protocol logic analyzer configured within automated test equipment (ATE) hardware
#75Electrical testing apparatus for spintronics devices
#76Systems and methods for bypass testing
#77Method for producing a semiconductor device by means of computer-aided development of test scenarios
#78ATE compatible high-efficient functional test
#79Test and measurement device and operating method
#80Automatic device detection and connection verification
#81Testing device and testing method
#82Converged test platforms and processes for class and system testing of integrated circuits
#83Systems and methods for dynamically reconfiguring automatic test equipment
#84Test architecture with an FPGA based test board to simulate a DUT or end-point
#85Method and system for acquisition of test data
#86Universal automated testing of embedded systems
#87Automated test equipment for combined signals
#88Automatic test equipment (ATE) platform translation
#89Configuration and testing method and system for FPGA chip using bumping process
#90Self-contained reconfigurable personal laboratory
#91Test equipment, method for operating a test equipment and computer program
#92Test device and test system having the same
#93Test devices and test systems
#94Magnetic field programming of electronic devices on a wafer
#95Tester for integrated circuits on a silicon wafer and integrated circuit
#96Test IP-based A.T.E. instrument architecture
#97Controlling a test run on a device under test without directly controlling the test equipment within a vendor test platform testing the device under test
#98On-chip field testing methods and apparatus
#99Testing apparatus for electronic device
#100Structural testing of integrated circuits
#101System for testing an integrated circuit of a device and its method of use
#102Simultaneous transition testing of different clock domains in a digital integrated circuit
#103API-based pattern-controlled test on an ATE
#104RF probe
#105Integrated circuit testing interface on automatic test equipment
#106Executing code on a test instrument in response to an event
#107Universal device multi-function test apparatus
#108Tester to simultaneously test different types of semiconductor devices and test system including the same
#109Probe card partition scheme
#110Testing an integrated circuit
#111Multi-core processor having disabled cores
#112Using shared pins in a concurrent test execution environment
#113Embedded tester
#114Semiconductor inspection apparatus and semiconductor inspection method
#115Testing device
#116Built-off test device and test system including the same
#117Built-in-self-test using embedded memory and processor in an application specific intergrated circuit
#118Real-time rule engine for adaptive testing of integrated circuits
#119Real-time rule engine for adaptive testing of integrated circuits
#120Test apparatus and test method
#121Solution for full speed, parallel DUT testing
#122Packetizing JTAG across industry standard interfaces
#123Digital integrated circuit testing and characterization system and method
#124Test instrument having a configurable interface
#125Programmable test instrument
#126Probe card partition scheme
#127Built-in-self-test using embedded memory and processor in an application specific integrated circuit
#128Semiconductor module, test system and method employing the same
#129SIGNAL TRANSMISSION APPARATUS AND SEMICONDUCTOR TEST APPARATUS USING THE SAME
#130System for testing an integrated circuit of a device and its method of use
#131Method of testing asynchronous modules in semiconductor device
#132Flexible storage interface tester with variable parallelism and firmware upgradeability
#133Tester to test a plurality of semiconductor devices and test system including the same
#134METHOD OF TESTING AN OBJECT AND APPARATUS FOR PERFORMING THE SAME
#135Built-in-self-test using embedded memory and processor in an application specific integrated circuit
#136METHOD OF TESTING INTEGRATED CIRCUITS
#137Re-configurable test circuit, method for operating an automated test equipment, apparatus, method and computer program for setting up an automated test equipment
#138Process for making an electric testing of electronic devices
#139Built-in self-test using embedded memory and processor in an application specific integrated circuit
#140TEST APPARATUS, TEST METHOD, AND PHASE SHIFTER
#141Built-off test device and test system including the same
#142Using pattern generators to control flow of data to and from a semiconductor device under test
#143Test apparatus of semiconductor integrated circuit and method using the same
#144Method of sharing a test resource at a plurality of test sites, automated test equipment, handler for loading and unloading devices to be tested and test system
#145System for testing an integrated circuit of a device and its method of use
#146Signal processing apparatus, test system, distortion detecting apparatus, signal compensation apparatus, analytic signal generating apparatus, recording medium and analytic signal generating method
#147Distortion identification apparatus, test system, recording medium and distortion identification method
#148Semiconductor testing device, semiconductor device, and testing method
#149SEMICONDUCTOR TEST APPARATUS AND TEST METHOD FOR SEMICONDUCTOR DEVICE
#150Electronic device, host apparatus, communication system, and recording medium
#151System and method for checking analog circuit with digital checker
#152Test equipment and semiconductor device
#153Data processor having disabled cores
#154Method and product for testing a device under test
#155Electrical tester setup and calibration device
#156Testing system for a device under test
#157Test apparatus of semiconductor integrated circuit and method using the same
#158System for testing an integrated circuit of a device and its method of use
#159GENERATION OF TEST SPECIFICATIONS BASED ON MEASURED DATA POINTS
#160Methodology and system to set JTAG interface
#161Built-in self-test using embedded memory and processor in an application specific integrated circuit
#162System and method for testing information handling system components
#163TEST APPARATUS AND DEVICE INTERFACE
#164Apparatus for testing electronic devices
#165MEASUREMENT DEVICE, METHOD, PROGRAM, AND RECORDING MEDIUM
#166Method and system for controlling multiple physical pin electronics channels in a semiconductor test head
#167Method for optimizing probe card design
#168Mapping logic for controlling loading of the select ram of an error data crossbar multiplexer
#169Memory test engine
#170Testing apparatus, testing method, jitter filtering circuit, and jitter filtering method
#171Method and apparatus for determining which timing sets to pre-load into the pin electronics of a circuit test system, and for pre-loading or storing said timing sets
#172Wireless test system
#173Testing system using configurable integrated circuit
#174Configurable voltage regulator
#175Configurable voltage regulator
#176Test apparatus with tester channel availability identification
#177Test device with test parameter adaptation
#178Fasttest module
#179Site-aware objects
#180Automatic test equipment operating architecture
#181Automatic test equipment operating architecture
#182Test apparatus and setting method therefor
#183Method for managing semiconductor characteristic evaluation apparatus and computer program therefor
#184Test program set obsolescence mitigation through software and automatic test equipment system processes
#185Method and system for performing installation and configuration management of tester instrument modules
#186Clock transferring apparatus for synchronizing input data with internal clock and test apparatus having the same
#187Semiconductor device with termination resistor circuit
#188Integrated circuit die including a temperature detection circuit, and system and methods for calibrating the temperature detection circuit
#189System and method for linking and loading compiled pattern data
#190System and method for linking and loading compiled pattern data
#191Testing apparatus
#192Automatic test equipment operating architecture
#193Test apparatus and writing control circuit
#194Compensation for test signal degradation due to DUT fault
#195Wireless test system
#196Circuit and method for testing a circuit having memory array and addressing and control unit
#197System and method for performing concurrent mixed signal testing on a single processor
#198Universal test chiplet
#199Dynamically configurable system-on-chip network
#200Test arrangement for adjusting a setup of testing a device under test, a method of operating the test arrangement, and a non-transitory computer-readable recording medium
#201Multi-function electronic device testing