Apparatus and method for using instruction translation look-aside buffers in the branch target buffer

METHOD, SYSTEM, AND APPARATUS FOR PAGE SIZING EXTENSION

Prefetch mechanism for a cache structure

MICROPROCESSOR ARCHITECTURE HAVING ALTERNATIVE MEMORY ACCESS PATHS

CLASS OF SERVICE

Secure modular devices

SERDES link training

Memory management unit (MMU) for accessing borrowed memory

Memory access control

Controlling memory accesses using a tag-guarded memory access operation

Apparatus and method for efficient process-based compartmentalization

Physical memory compression

Backward compatibility testing of software in a mode that disrupts timing

Memory management

Memory allocation for processing-in-memory operations

Generating, maintaining, or utilizing a compressed logical-to-physical table based on sequential writes

Memory accessor invailidation

Supporting secure memory intent

Read-write page replication for multiple compute units

Secure memory translations

Handling guard tag loss

Processing pipeline with first and second processing modes having different performance or energy consumption characteristics

VIRTUAL REGISTER FILE

System and method for handling address translation invalidations using an address translation invalidation probe

Apparatus and method for efficient process-based compartmentalization

Coherency tracking apparatus and method for an attached coprocessor or accelerator

Data reading and writing processing from and to a semiconductor memory and a memory of a host device by using first and second interface circuits

Arbitration scheme for coherent and non-coherent memory requests

PAGE TABLE MAPPING MECHANISM

Flexible storage and optimized search for multiple page sizes in a translation lookaside buffer

Memory system for binding data to a memory namespace

Enhanced page information co-processor

Adaptive cache management based on programming model information

Checker cores for fault tolerant processing

Real time input/output address translation for virtualized systems

Data compression and encryption based on translation lookaside buffer evictions

Process dedicated in-memory translation lookaside buffers (TLBs) (mTLBs) for augmenting memory management unit (MMU) TLB for translating virtual addresses (VAs) to physical addresses (PAs) in a processor-based system

Latency hiding for caches

Zero latency prefetching in caches

Allocating and accessing memory pages with near and far memory blocks from heterogenous memories

Paging of external memory

Systems and methods for data processing

Techniques for an efficient fabric attached memory

Handling memory requests

Software-hardware memory management modes

Non-stalling, non-blocking translation lookaside buffer invalidation

Translation lookaside buffer prewarming

Processors, methods, systems, and instructions to protect shadow stacks

Temporarily suppressing processing of a restrained storage operand request

Translation load instruction with access protection

SECURE AND EFFICIENT MICROCODE(UCODE) HOT-UPGRADE FOR BARE METAL CLOUD

Translation lookaside buffer in memory

Memory management unit, address translation method, and processor

Techniques for storing data and tags in different memory arrays

Hardware implementations of a quasi-cyclic syndrome decoder

Mapping non-typed memory access to typed memory access

Memory system for binding data to a memory namespace

Page table hooks to memory types

Accessing stored metadata to identify memory devices in which data is stored

System, apparatus and method for segmenting a memory array

Optimizing access to page table entries in processor-based devices

FILTERING INVALIDATION REQUESTS

Apparatus and method for memory management in a graphics processing environment

Networked input/output memory management unit

Retaining cache entries of a processor core during a powered-down state

MEMORY MANAGEMENT FOR A HIERARCHICAL MEMORY SYSTEM

CONTROLLER FOR LOCKING OF SELECTED CACHE REGIONS

Hardware for split data translation lookaside buffers

Cache structure using a logical directory

Epoch-based determination of completion of barrier termination command

Random tag setting instruction for a tag-guarded memory system

SYSTEMS AND METHODS FOR IMPLEMENTING A RANDOM ACCESS AUGMENTED MACHINE PERCEPTION AND DENSE ALGORITHM INTEGRATED CIRCUIT

HARDWARE LOAD HARDENING FOR SPECULATIVE SIDE-CHANNEL ATTACKS

Memory protection with hidden inline metadata to indicate data type

Speculative address translation requests pertaining to instruction cache misses

Operational context subspaces

High-frequency and low-power L1 cache and associated access technique

Method and apparatus to control the use of hierarchical branch predictors based on the effectiveness of their results

Method and apparatus to process SHA-2 secure hashing algorithm

Systems and methods for data processing

Wireless memory interface

Inter operating system memory services over communication network connections

Translation lookaside buffer invalidation for merged invalidation requests across power boundaries

Memory management unit (MMU) for accessing borrowed memory

Fine grain data migration to or from borrowed memory

Intelligent content migration with borrowed memory

Address translation technologies

Application processor, system-on chip and method of operating memory management unit

Apparatuses and methods for accessing hybrid memory system

Securing memory accesses in a virtualized environment

Processing system with round-robin mechanism and its memory access method

PROCESSING SYSTEM FOR SCHEDULING AND ITS MEMORY ACCESS METHOD

Process scheduling in a processing system having at least one processor and shared hardware resources

Memory access compression using clear code for tile pixels

Packet processing device, packet processing method, and recording medium

METHOD ENABLING VIRTUAL PAGES TO BE ALLOCATED WITH NONCONTIGUOUS BACKING PHYSICAL SUBPAGES

Shared accelerator memory systems and methods

Memory management apparatus and method for managing different page tables for different privilege levels

Using multiple memory elements in an input-output memory management unit for performing virtual address to physical address translations

Data processing

Storage system and method for accessing same

Apparatus and method

Memory system using SRAM with flag information to identify unmapped addresses

Cache management operations using streaming engine

INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND STORAGE MEDIUM

Restricted speculative execution mode to prevent observable side effects

Secure processor and a program for a secure processor

Virtualized-in-hardware input output memory management

Unified addressable memory

Processor to detect redundancy of page table walk

Systems and methods for implementing random access memory in a flow-based machine perception and dense algorithm integrated circuit based on computing and coalescing of indices

Cache replacement based on translation lookaside buffer evictions

Real time input/output address translation for virtualized systems

METHOD, SYSTEM, AND APPARATUS FOR PAGE SIZING EXTENSION

CPU-efficient cache replacment with two-phase eviction

Programmable address range engine for larger region sizes

Secure memory repartitioning technologies

APPARATUS AND METHOD FOR EFFICIENT MANAGEMENT OF MULTI-LEVEL MEMORY

Managing fusion of memory regions and ownership attributes for fused memory regions

MECHANISM FOR ISSUING REQUESTS TO AN ACCELERATOR FROM MULTIPLE THREADS

Translation system for finer grain memory architectures

Software translation prefetch instructions

Method for migrating CPU state from an inoperable core to a spare core

Memory controller and memory page management method

Interruptible translation entry invalidation in a multithreaded data processing system

Memory system and operating method thereof

Steering tag support in virtualized environments

Translation entry invalidation in a multithreaded data processing system

Handling effective address synonyms in a load-store unit that operates without address translation

Management of the untranslated to translated code steering logic in a dynamic binary translation based processor

Hardware unit for reverse translation in a processor

Cryptographic computing engine for memory load and store units of a microarchitecture pipeline

Address translation data invalidation

Servicing CPU demand requests with inflight prefetches

Realm identifier comparison for translation cache lookup

System for address mapping and translation protection

Memory system for storing map data in host memory and operating method of the same

Distributed address translation in a multi-node interconnect fabric

Partitioning TLB or cache allocation

Memory addressing

Logic-executing ring buffer

INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND COMPUTER PROGRAM PRODUCT

Technologies for execute only transactional memory

Persistent memory cleaning

Method for min-max computation in associative memory

Method and apparatus for an efficient TLB lookup

Fine granularity translation layer for data storage devices

Method, system, and apparatus for stress testing memory translation tables

I/O device and computing host interoperation

TLB shootdowns for low overhead

Method, apparatus, and system for reducing pipeline stalls due to address translation misses

Apparatus and method for performing address translation using buffered address translation data

MEMORY ACCESS METHOD AND COMPUTER SYSTEM

Apparatus and method for engaging a plurality of memory systems with each other

Managing partial superblocks in a NAND device

Secure address translation services using message authentication codes and invalidation tracking

Testing hierarchical address translation with context switching and overwritten table definition data

Apparatus, methods, and systems for low latency communication in a configurable spatial accelerator

Cache partitioning mechanism

Memory-mapped interface to message-passing computing systems

Cache-based trace replay breakpoints using reserved tag field bits

Systems and methods to predict load data values

Apparatus and method for memory management in a graphics processing environment

Hardware-based virtual-to-physical address translation for programmable logic masters in a system on chip

Temporarily suppressing processing of a restrained storage operand request

Memory array page table walk

Processors, methods, systems, and instructions to load multiple data elements to destination storage locations other than packed data registers

Arithmetic processing device, information processing apparatus, and method for controlling arithmetic processing device

Dynamically adapting mechanism for translation lookaside buffer shootdowns

MMIO addressing using a translation lookaside buffer

Arithmetic processor, information processing apparatus, and control method of arithmetic processor

Processor with processor memory pairs for improved process switching and methods thereof

Arithmetic processing apparatus and control method for arithmetic processing apparatus

Arithmetic processing apparatus and method of controlling arithmetic processing apparatus

Increasing the scope of local purges of structures associated with address translation

System, apparatus and method for segmenting a memory array

TLB device supporting multiple data streams and updating method for TLB module

Enhanced address space layout randomization

Zero test time memory using background built-in self-test

Certifiable deterministic system software framework for hard real-time safety-critical applications in avionics systems featuring multi-core processors

Integrated circuit and data processing system supporting address aliasing in an accelerator

Translation of virtual addresses to physical addresses using translation lookaside buffer information

Integrated circuit and data processing system having a configurable cache directory for an accelerator

Translation invalidation in a translation cache serving an accelerator

Integrated circuit and data processing system supporting attachment of a real address-agnostic accelerator

Method and apparatus to process SHA-2 secure hashing algorithm

Technologies for transmit scheduler dynamic configurations

Maintaining processor resources during architectural events

Page tables for granular allocation of memory pages

Supporting secure memory intent

Storage device buffer in system memory space

Apparatus and method for accessing an address translation cache

Semiconductor memory device for controlling an address for temperature management

Executing load-store operations without address translation hardware per load-store unit port

System and method for retaining DRAM data when reprogramming reconfigureable devices with DRAM memory controllers incorporating a data maintenance block

Dynamic address translation with access control in an emulator environment

Fast page fault handling process implemented on persistent memory

Apparatus and method for an early page predictor for a memory paging subsystem

Apparatus and method for handling page invalidate requests in an address translation cache

Memory system with block rearrangement to secure a free block based on read valid first and second data

NETWORK INTERFACE DEVICE, INFORMATION PROCESSING DEVICE HAVING PLURAL NODES INCLUDING NETWORK INTERFACE DEVICE, AND METHOD FOR TRANSMITTING TRANSMISSION DATA BETWEEN NODES OF INFORMATION PROCESSING DEVICE

Suspending translation look-aside buffer purge execution in a multi-processor environment

Facilitating access to memory locality domain information

Secure control flow prediction

Decoupling memory metadata granularity from page size

System protecting caches from side-channel attacks

Reducing conflicts in direct mapped caches

Zone-SDID mapping scheme for TLB purges

Efficient memory deduplication by hypervisor initialization

Architectural enhancements for computing systems having artificial intelligence logic disposed locally to memory

Coalescing adjacent gather/scatter operations

Paging of external memory

SCALABLE APPLICATION-CUSTOMIZED MEMORY COMPRESSION

Method and system for operating NAND flash physical space to extend memory capacity

Memory address translation using stored key entries

Mode-selectable processor for execution of a single thread in a first mode and plural borrowed threads in a second mode

Secure processor and a program for a secure processor

Adaptive tablewalk translation storage buffer predictor

Memory access compression using clear code for tile pixels

Translation look-aside buffer and prefetch indicator

Apparatus and method for shared resource partitioning through credit management

Methods and apparatus of anomalous memory access pattern detection for translational lookaside buffers

TLB device supporting multiple data streams and updating method for TLB module

Scalable memory interface for graphical processor unit

Active side-channel attack prevention

Mechanism to support variable size page translations

Adaptive buffer latching to reduce display janks caused by variable buffer allocation time

Fast invalidation in peripheral component interconnect (PCI) express (PCIe) address translation services (ATS)

MEMORY MANAGEMENT UNIT PERFORMANCE THROUGH CACHE OPTIMIZATIONS FOR PARTIALLY LINEAR PAGE TABLES OF FRAGMENTED MEMORY

Processing vectorized guest physical address translation instructions

Managing partial superblocks in a NAND device

Unblock instruction to reverse page block during paging

Search memory

Single instruction multiple data page table walk scheduling at input output memory management unit

Selective suppression of instruction translation lookaside buffer (ITLB) access

Selective suppression of instruction cache-related directory access

TRANSLATION PINNING IN TRANSLATION LOOKASIDE BUFFERS

Method, system, and apparatus for stress testing memory translation tables

Detecting malicious software by inspecting table look-aside buffers

Translation system for finer grain memory architectures

Translation system for finer grain memory architectures

TRANSLATION TABLE ENTRY PREFETCHING IN DYNAMIC BINARY TRANSLATION BASED PROCESSOR

Servicing CPU demand requests with inflight prefetches

Non-blocking directory-based cache coherence

DIRECT MEMORY ADDRESSES FOR ADDRESS SWAPPING BETWEEN INLINE MEMORY MODULES

Handling contingent and non-contingent memory access program instructions making use of disable flag

Optimizing headless virtual machine memory management with global translation lookaside buffer shootdown

Lightweight address translation for page migration and duplication

Dynamic address translation for a virtual machine

MANAGEMENT OF THE UNTRANSLATED TO TRANSLATED CODE STEERING LOGIC IN A DYNAMIC BINARY TRANSLATION BASED PROCESSOR

PAGE TRANSLATION PREFETCH MECHANISM

Memory address translation

Performing maintenance operations

Handling memory requests

Resource access method applied to computer and computer

Memory address translation management

Safe userspace device access for network function virtualization using an IOMMU to map supervisor memory to a reserved range of application virtual addresses

Address translation prior to receiving a storage reference using the address to be translated

Optimizing page table manipulations

Single call to perform pin and unpin operations

Affinity domain-based garbage collection

Address translation for scalable linked devices

Facilitating access to memory locality domain information

Memory domains protection method and apparatus with composite protection key numbers

Capability enforcement controller

Retaining cache entries of a processor core during a powered-down state

IMAGE PROCESSING APPARATUS AND IMAGE DATA PROCESSING METHOD COOPERATING WITH FRAME BUFFER

Using a first-in-first-out (FIFO) wraparound address lookup table (ALT) to manage cached data

Memory-mapped interface for message passing computing systems

Zero latency prefetching in caches

Increasing the scope of local purges of structures associated with address translation

Method for accessing entry in translation lookaside buffer TLB and processing chip

Address translation for sending real address to memory subsystem in effective address based load-store unit

Address translation for sending real address to memory subsystem in effective address based load-store unit

Executing load-store operations without address translation hardware per load-store unit port

Effective address based load store unit in out of order processors

Handling effective address synonyms in a load-store unit that operates without address translation

Handling effective address synonyms in a load-store unit that operates without address translation

Handling effective address synonyms in a load-store unit that operates without address translation

Handling effective address synonyms in a load-store unit that operates without address translation

Effective address based load store unit in out of order processors

Indexing entries of a storage structure shared between multiple threads

CACHE BEHAVIOR FOR SECURE MEMORY REPARTITIONING SYSTEMS

TECHNIQUES TO PROVIDE ACCESS PROTECTION TO SHARED VIRTUAL MEMORY

Method and electronic device for accessing data

Open-addressing probing barrier

Secure memory repartitioning technologies

Cache management operations using streaming engine

Partially deactivated application with termination protection

Hypervisor direct memory access

TRANSACTION DISPATCHER FOR MEMORY MANAGEMENT UNIT

Intelligently partitioning data cache to allocate space for translation entries

HYPERVISOR MEMORY CACHE INVALIDATION

Nested hypervisor memory virtualization

Translation lookaside buffer management method and multi-core processor

Apparatus and method for efficient utilisation of an address translation cache

Ensuring forward progress for nested translations in a memory management unit

Ensuring forward progress for nested translations in a memory management unit

Reducing translation latency within a memory management unit using external caching structures

Reducing translation latency within a memory management unit using external caching structures