190279 ⎘
Accessing, addressing or allocating within memory systems or architectures; Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems; Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
Method to manage guest address space trusted by virtual machine monitor
#602Method for min-max computation in associative memory
#603Methods, systems and apparatus for supporting wide and efficient front-end operation with guest-architecture emulation
#604Techniques for enclave confidentiality management
#605APPARATUS AND METHOD INCLUDING A THERMAL NOISE ADAPTIVE SCHEDULER FOR CONTROLLING A QUANTUM COMPUTER
#606Avoiding asynchronous enclave exits based on requests to invalidate translation lookaside buffer entries
#607Process-based multi-key total memory encryption
#608Virtual transfer of data between memory and storage domains
#609Pause communication from I/O devices supporting page faults
#610Mitigation of cache-latency based side-channel attacks
#611Management of coherent links and multi-level memory
#612Method and apparatus for multi-level memory early page demotion
#613Serdes link training
#614Dynamic thread mapping
#615System Memory Management Unit Architecture For Consolidated Management Of Virtual Machine Stage 1 Address Translations
#616Private caching for thread local storage data access
#617Method and apparatus for an efficient TLB lookup
#618Memory address translation
#619Filtering of redundantly scheduled write passes
#620Unified addressable memory
#621MECHANISMS TO ENFORCE SECURITY WITH PARTIAL ACCESS CONTROL HARDWARE OFFLINE
#622Apparatuses and methods for a processor architecture
#623Supporting soft reboot in multi-processor systems without hardware or firmware control of processor state
#624Searching varying selectable physical blocks of entries within a content-addressable memory
#625SEMICONDUCTOR DEVICE
#626Method for switching address spaces via an intermediate address space
#627Memory type which is cacheable yet inaccessible by speculative instructions
#628Providing hardware-based translation lookaside buffer (TLB) conflict resolution in processor-based systems
#629Memory Sharing For Virtual Machines
#630INPUT/OUTPUT COMPUTER SYSTEM INCLUDING HARDWARE ASSISTED AUTOPURGE OF CACHE ENTRIES ASSOCIATED WITH PCI ADDRESS TRANSLATIONS
#631Technologies for protecting virtual machine memory
#632Management of data transaction from I/O devices
#633Management of data transaction from I/O devices
#634Suspending translation look-aside buffer purge execution in a multi-processor environment
#635Suspending translation look-aside buffer purge execution in a multi-processor environment
#636Sharing virtual and real translations in a virtual cache
#637Switching between single-level and two-level page table translations
#638Suspending translation look-aside buffer purge execution in a multi-processor environment
#639Sharing virtual and real translations in a virtual cache
#640Memory management supporting huge pages
#641Cache structure using a logical directory
#642Cache structure using a logical directory
#643Maintaining processor resources during architectural events
#644Memory management for a hierarchical memory system
#645Transmission of a message based on a determined cognitive context
#646Data processor
#647Global variable migration via virtual memory overlay technique for multi-version asynchronous dynamic software update
#648Input/output translation lookaside buffer prefetching
#649Virtual register file
#650Method and apparatus for hardware management of multiple memory pools
#651Method and apparatus for processing instructions using processing-in-memory
#652Tracking and managing translation lookaside buffers
#653Kernel-assisted inter-process data transfer
#654Incremental snapshot based technique on paged translation systems
#655Methods for scheduling read commands and apparatuses using the same
#656Safe execution of virtual machine callbacks in a hypervisor
#657Translation lookaside buffer switch bank
#658Electronic device and method for managing memory thereof
#659Managed hardware accelerator address translation fault resolution utilizing a credit
#660Managed hardware accelerator address translation fault resolution utilizing a credit
#661Event triggered programmable prefetcher
#662Page migration with varying granularity
#663Methods and systems including a memory-side memory controller configured to interpret capabilities to provide a requested dataset to a central processing unit
#664Fully virtualized TLBs
#665Memory access compression using clear code for tile pixels
#666Pseudo-invalidating dynamic address translation (DAT) tables of a DAT structure associated with a workload
#667Permuted memory access mapping
#668Silent active page migration faults
#669MAINTAINING AGENT INCLUSIVITY WITHIN A DISTRIBUTED MMU
#670MAINTAINING AGENT INCLUSIVITY WITHIN A DISTRIBUTED MMU
#671TRANSLATE FURTHER MECHANISM
#672Apparatus and method for memory management in a graphics processing environment
#673Method and apparatus for accessing data stored in a storage system that includes both a final level of cache and a main memory
#674Operation of a multi-slice processor implementing exception handling in a nested translation environment
#675Translation lookaside buffer in a switch
#676Zero test time memory using background built-in self-test
#677Reducing conflicts in direct mapped caches
#678Dynamic fill policy for a shared cache
#679Kernel same-page merging for encrypted memory
#680Asynchronously clearing page frames
#681Partitioned memory with locally aggregated copy pools
#682Partitioned memory with locally aggregated copy pools
#683Storage system, computer program product, and method for managing a hybrid memory device system
#684Allocating and accessing memory pages with near and far memory blocks from heterogeneous memories
#685Management device, information processing device, and management method
#686Storage device and error correction method for storage device
#687Streaming translation lookaside buffer
#688Sharing translation lookaside buffer resources for different traffic classes
#689Per-page control of physical address space distribution among memory modules
#690Safe userspace device access for network function virtualization using an IOMMU to map supervisor memory to a reserved range of application virtual addresses
#691Technique for efficient utilisation of an address translation cache
#692Supporting secure memory intent
#693Memory array page table walk
#694Controlling access by IO devices to pages in a memory in a computing device
#695Dynamic address translation table allocation
#696Selecting a default page size in a variable page size TLB
#697Linear memory address transformation and management
#698Variable translation-lookaside buffer (TLB) indexing
#699Firmware or hardware component assist for memory mapped I/O
#700SYNCHRONIZING A TRANSLATION LOOKASIDE BUFFER WITH AN EXTENDED PAGING TABLE
#701Synchronizing a translation lookaside buffer with an extended paging table
#702Temporarily suppressing processing of a restrained storage operand request
#703Physical address management in solid state memory by tracking pending reads therefrom
#704SYSTEM MEMORY MIGRATION
#705Processors, methods, systems, and instructions to check and store indications of whether memory addresses are in persistent memory
#706Configurable skewed associativity in a translation lookaside buffer
#707SYSTEM AND METHOD FOR RETAINING DRAM DATA WHEN REPROGRAMMING RECONFIGURABLE DEVICES WITH DRAM MEMORY CONTROLLERS INCORPORATING A DATA MAINTENANCE BLOCK COLOCATED WITH A MEMORY MODULE OR SUBSYSTEM
#708Memory management in virtualized computing systems having processors with more than two hierarchical privilege levels
#709Time-restricted access to file data
#710Emulating mode-based execute control for memory pages in virtualized computing systems
#711Memory management
#712System, apparatus and method for low overhead control transfer to alternate address space in a processor
#713Zeroing a cache line
#714Transmitting contents of an operation field to a media controller
#715Apparatuses, methods, and systems to share translation lookaside buffer entries
#716Trapless shadow page tables
#717Batched memory page hinting
#718Reduced stack usage in a multithreaded processor
#719Apparatus and method for transferring data between address ranges in memory
#720Lockless free memory ballooning for virtual machines
#721Memory overcommit by speculative fault
#722Protecting memory storage content
#723Bus-device-function address space mapping
#724Input/output translation lookaside buffer (IOTLB) quality of service (QoS)
#725Programmable memory transfer request processing units
#726Cache memory architecture and policies for accelerating graph algorithms
#727Method to share a coherent accelerator context inside the kernel
#728Method to share a coherent accelerator context inside the kernel
#729Computing methods and apparatuses with graphics and system memory conflict check
#730Identifying stale entries in address translation cache
#731METHOD AND APPARATUS FOR MANAGING RESOURCE ACCESS CONTROL HARDWARE IN A SYSTEM-ON-CHIP DEVICE
#732Method and apparatus for power reduction in a multi-threaded mode
#733Dynamic address translation table allocation
#734Page table entry caching for virtual device emulation
#735Apparatus and method for maintaining address translation data within an address translation cache
#736Memory system and operating method thereof
#737Latency by persisting data relationships in relation to corresponding data in persistent memory
#738Apparatus and method for maintaining address translation data within an address translation cache
#739HARDWARE-BASED SHARED DATA COHERENCY
#740PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS TO DETERMINE PAGE GROUP IDENTIFIERS, AND OPTIONALLY PAGE GROUP METADATA, ASSOCIATED WITH LOGICAL MEMORY ADDRESSES
#741Processors, methods, systems, and instructions to load multiple data elements to destination storage locations other than packed data registers
#742Data writing processing into memory of a semiconductor memory device by using a memory of a host device
#743Toggling modal transient memory access state
#744Dynamic address translation with access control in an emulator environment
#745Translation lookaside buffer
#746Reducing page invalidation broadcasts in virtual storage management
#747Interrupt-vector translation lookaside buffer
#748Memory management supporting huge pages
#749System and method for implementing an efficient large system page invalidation
#750Method and device for partitioning association table in distributed database
#751Selective purging of PCI I/O address translation buffer
#752Method and device for accessing a cache memory
#753Host page management using active guest page table indicators
#754Host-based resetting of active use of guest page table indicators
#755Enhance memory access permission based on per-page current privilege level
#756Synchronizing a translation lookaside buffer with an extended paging table
#757Linear to physical address translation with support for page attributes
#758Marking storage keys to indicate memory used to back address translation structures
#759Apparatus and method for shared resource partitioning through credit management
#760Address control circuit capable of setting address rapidly and method of setting address after power-on reset, the address control circuit providing protection against over-voltage
#761Updating least-recently-used data for greater persistence of higher generality cache entries
#762Selective suppression of instruction cache-related directory access
#763Compressed freezer files
#764Physical address management in solid state memory
#765Selective suppression of instruction translation lookaside buffer (ITLB) access
#766Transparent routers to provide services
#767Controlling access to pages in a memory in a computing device
#768Memory space management
#769Systems and methods for accessing a unified translation lookaside buffer
#770TECHNOLOGIES FOR VIRTUAL MACHINE MIGRATION
#771Selective purging of entries of structures associated with address translation in a virtualized environment
#772SELECTIVE PURGING OF GUEST ENTRIES OF STRUCTURES ASSOCIATED WITH ADDRESS TRANSLATION
#773Increasing the scope of local purges of structures associated with address translation
#774Marking to indicate memory used to back address translation structures
#775Host page management using active guest page table indicators
#776Marking storage keys to indicate memory used to back address translation structures
#777Reducing over-purging of structures associated with address translation using an array of tags
#778Managing memory used to back address translation structures
#779Marking page table/page status table entries to indicate memory used to back address translation structures
#780Reducing over-purging of structures associated with address translation
#781Host-based resetting of active use of guest page table indicators
#782System and method for identifying pendency of a memory access request at a cache entry
#783Delaying purging of structures associated with address translation
#784NON-TRANSITORY COMPUTER-READABLE STORAGE MEDIUM, MEMORY MANAGEMENT DEVICE, AND MEMORY MANAGING METHOD
#785Reducing purging of structures associated with address translation
#786Supporting data compression using match scoring
#787Systems, Apparatuses, and Methods for Platform Security
#788Apparatus and method for performing address translation
#789Memory system and method for wear-leveling by swapping memory cell groups
#790Accessing physical memory from a CPU or processing element in a high performance manner
#791Computer system including synchronous input/output and hardware assisted purge of address translation cache entries of synchronous input/output transactions
#792Method and logic for maintaining performance counters with dynamic frequencies
#793Incremental snapshot based technique on paged translation systems
#794Method and apparatus for reducing TLB shootdown overheads in accelerator-based systems
#795Microcontroller for memory management unit
#796Managing virtual-address caches for multiple memory page sizes
#797Maintaining consistency between address translations in a data processing system
#798In-memory attack prevention
#799Compression and caching for logical-to-physical storage address mapping tables
#800TLB shootdowns for low overhead
#801Memory controller, information processing system, and memory extension area management method
#802Information processing device, method, and non-transitory computer-readable recording medium storing information processing program for loading code into reconfigurable integrated circuit
#803ADDRESS TRANSLATION WITHIN A VIRTUALISED SYSTEM BACKGROUND
#804Using multiple memory elements in an input-output memory management unit for performing virtual address to physical address translations
#805Embedded page size hint for page fault resolution
#806Memory pre-fetch for virtual memory
#807Apparatus and method for using fields in N-space translation of storage requests
#808System and method for memory synchronization of a multi-core system
#809System architecture for encrypting external memory
#810Managing cache coherence using information in a page table
#811Apparatus and method for processing data, including cache entry replacement performed based upon content data read from candidates selected using victim selection
#812IDENTIFYING PAGES IN A MIGRATION MANAGEMENT SYSTEM
#813Virtual memory page mapping overlays
#814Synchronous input/output computer system including hardware invalidation of synchronous input/output context
#815COMPUTING RESOURCE WITH MEMORY RESOURCE MEMORY MANAGEMENT
#816Memory controller with memory resource memory management
#817I/O device and computing host interoperation
#818Method and apparatus for use in accessing a memory
#819Method and apparatus for translation lookaside buffer with multiple compressed encodings
#820Dynamic page table edit control
#821Adapted block translation table (BTT)
#822Lightweight architecture for aliased memory operations
#823Data processing system having a coherency interconnect
#824Memory object tagged memory monitoring method and system
#825Method and apparatus for utilizing proxy identifiers for merging of store operations
#826Method for migrating CPU state from an inoperable core to a spare core
#827Technologies for a distributed hardware queue manager
#828Enhanced directed system management interrupt mechanism
#829Managing translation invalidation
#830Hardware-based translation lookaside buffer (TLB) invalidation
#831Processor and method for memory performance monitoring utilizing a monitor flag and first and second allocators for allocating virtual memory regions
#832Apparatus and method for low-overhead synchronous page table updates
#833Handling memory requests
#834Method for managing memory of virtual machine, physical host, PCIE device and configuration method thereof, and migration management device
#835Method for performing data updates
#836Adaptive extension of leases for entries in a translation lookaside buffer
#837Using leases for entries in a translation lookaside buffer
#838Data processing method, memory management unit, and memory control device
#839Implementing fault tolerance in computer system memory
#840Reconfigurable test access port with finite state machine control
#841PROCESSING DEVICE, INFORMATION PROCESSING APPARATUS, AND CONTROL METHOD OF PROCESSING DEVICE
#842Multi-range lookup in translation lookaside buffer
#843Digital perceptron
#844Systems and methods for secure multi-access of system firmware during pre-boot
#845Method and system for compressing data for a translation look aside buffer (TLB)
#846Coalescing adjacent gather/scatter operations
#847System for address mapping and translation protection
#848Microprocessor architecture having alternative memory access paths
#849Methods for scheduling read commands and apparatuses using the same
#850Synchronizing a translation lookaside buffer with page tables
#851Apparatus and method for supporting multiple cache features
#852METHOD AND DEVICE TO DISTRIBUTE CODE AND DATA STORES BETWEEN VOLATILE MEMORY AND NON-VOLATILE MEMORY
#853Routing direct memory access requests in a virtualized computing environment
#854Manipulation of virtual memory page table entries to form virtually-contiguous memory corresponding to non-contiguous real memory allocations
#855Region migration cache
#856Measuring address translation latency
#857Large-page optimization in virtual memory paging systems
#858Instruction set and micro-architecture supporting asynchronous memory access
#859Method and apparatus to shutdown a memory channel
#860Address translation for scalable virtualization of input/output devices
#861Apparatus and method for insertion and deletion in multi-dimensional to linear address space translation
#862Method, system, and apparatus for page sizing extension
#863Selective suppression of instruction translation lookaside buffer (ITLB) access
#864Frame buffer access tracking via a sliding window in a unified virtual memory system
#865Method, system, and apparatus for page sizing extension
#866Storage apparatus and storage control method
#867Storage device including nonvolatile memory device and controller, operating method of storage device, and method for accessing storage device
#868Cache memory
#869Data processing apparatus, and a method of handling address translation within a data processing apparatus
#870Techniques for a Write Transaction at a Storage Device
#871Translation entry invalidation in a multithreaded data processing system
#872Method and apparatus for sub-page write protection
#873Translation entry invalidation in a multithreaded data processing system
#874Centrally managed unified shared virtual address space
#875Method and apparatus for accessing data stored in a storage system that includes both a final level of cache and a main memory
#876Translation entry invalidation in a multithreaded data processing system
#877Transaction end plus commit to persistence instructions, processors, methods, and systems
#878Permutating vector data scattered in a temporary destination into elements of a destination register based on a permutation factor
#879Memory device and method for controlling memory device
#880Efficient address-to-symbol translation of stack traces in software programs
#881Techniques for storing data and tags in different memory arrays
#882High resolution timer expiry in live partition migration
#883Prefetching page access data for input surfaces requiring processing
#884Identifying stale entries in address translation cache
#885Identifying stale entries in address translation cache
#886Concurrent virtual storage management
#887Replaying memory transactions while resolving memory access faults
#888Identifying stale entries in address translation cache
#889Code placement using a dynamic call graph
#890Method to efficiently implement synchronization using software managed address translation
#891Apparatus and method for accelerating operations in a processor which uses shared virtual memory
#892Supervisory memory management unit
#893Invalidation of translation look-aside buffer entries by a guest operating system
#894Relocating a virtual address in a persistent memory
#895Optimizing page table manipulations
#896Hardware extensions for memory reclamation for concurrent data structures
#897Method and apparatus to process SHA-2 secure hashing algorithm
#898Method and apparatus to process SHA-2 secure hashing algorithm
#899Method and apparatus to process SHA-2 secure hashing algorithm
#900Method and apparatus to process SHA-2 secure hashing algorithm