Performing memory accesses while omitting unnecessary address translations

Efficient memory translator with variable size cache line coverage

Providing hardware support for shared virtual memory between local and remote physical memory

Processing diagnostic requests for direct block access storage devices

Startup reconstruction of logical-to-physical address translation data for solid state disks

Accessing logical-to-physical address translation data for solid state disks

Buffering of data transfers for direct access block devices

Cache synchronization for solid state disks

Logical-to-physical address translation for solid state disks

Dynamic storage of cache data for solid state disks

Processing host transfer requests for direct block access storage devices

Serial line protocol for embedded devices

Just in time compiler in spatially aware emulation of a guest computer instruction set

Host cell spatially aware emulation of a guest wild branch

Self initialized host cell spatially aware emulation of a computer instruction set

Page mapped spatially aware emulation of a computer instruction set

Method and system for combining page buffer list entries to optimize caching of translated addresses

Reducing broadcasts in multiprocessors

Translation look-aside buffer

Microprocessor with improved data stream prefetching

Coherency control system, coherency control apparatus and coherency control method

Processor and arithmatic operation method

I/O memory management unit including multilevel address translation for I/O and computation offload

TLB prefetching

Extended page size using aggregated small pages

Protecting a software component using a transition point wrapper

Processor and address translating method

Network use of virtual addresses without pinning or registration

AUTOMATICALLY USING SUPERPAGES FOR STACK MEMORY ALLOCATION

System and method to manage address translation requests

System and method to invalidate obsolete address translations

APPARATUS, SYSTEM, AND METHOD FOR CACHE COHERENCY ELIMINATION

Method and apparatus with data storage protocols for maintaining consistencies in parallel translation lookaside buffers

Shared virtual memory between a host and discrete graphics device in a computing system

Systems and methods for utilizing an extended translation look-aside buffer having a hybrid memory structure

Synchronizing a translation lookaside buffer with page tables

Partitioned replacement for cache memory

Methods and apparatus for fast context switching in a virtualized system

Translation look-aside buffer with a tag memory and method therefor

Translation lookaside buffer (TLB) with reserved areas for specific sources

Store prefetching via store queue lookahead

Method and apparatus for determining cache storage locations based on latency requirements

RISC PROCESSOR DEVICE AND ITS INSTRUCTION ADDRESS CONVERSION LOOKING-UP METHOD

Large memory pages for shared libraries

Dynamic translation in the presence of intermixed code and data

Circuits and methods for dual redundant register files with error detection and correction mechanisms

Circuits and methods for detection of soft errors in cache memories

Circuits and methods for processors with multiple redundancy techniques for mitigating radiation errors

Techniques for cache injection in a processor system based on a shared state

SEMICONDUCTOR INTEGRATED CIRCUIT, INFORMATION PROCESSING DEVICE, AND CONTROL METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT

Control of on-die system fabric blocks

Method and apparatus for tracking enregistered memory locations

Virtualization system using hardware assistance for shadow page table coherence

Prefetch engine based translation prefetching

Opportunistic improvement of MMIO request handling based on target reporting of space requirements

Apparatus and method to translate virtual addresses to physical addresses in a base plus offset addressing mode

Accessing memory locations for paged memory objects in an object-addressed memory system

Software table walk during test verification of a simulated densely threaded network on a chip

Translate and verify instruction for a processor

Program correlation message generation for debug

Method for debugger initiated coherency transactions using a shared coherency manager

Unified cache structure that facilitates accessing translation table entries

Fast address translation for linear and circular modes

Providing address range coherency capability to a device

Administering registered virtual addresses in a hybrid computing environment including maintaining a cache of ranges of currently registered virtual addresses

SEMICONDUCTOR INTEGRATED CIRCUIT AND ADDRESS TRANSLATION METHOD

Mapping address table maintenance in a memory device

Metaphysical address space for holding lossy metadata in hardware

Optimization for safe elimination of weak atomicity overhead

Method and apparatus for reallocating memory content

Virtualised interface functions

Processor with coprocessor interfacing functional unit for forwarding result from coprocessor to retirement unit

Arrangements having security protection

METHOD AND SYSTEM FOR EFFICIENT CACHE LOCKING MECHANISM

Method and apparatus for inclusion of TLB entries in a micro-op cache of a processor

Data structure for enforcing consistent per-physical page cacheability attributes

Display refresh

On-the fly TLB coalescing

Arithmetic processing unit and control method for evicting an entry from a TLB to another TLB

Indexing a translation lookaside buffer (TLB)

Calculator and TLB control method

System and method for concurrently managing memory access requests

Hot memory block table in a solid state storage device

NON-VOLATILE SEMICONDUCTOR MEMORY DRIVE, INFORMATION PROCESSING APPARATUS AND DATA ACCESS CONTROL METHOD OF THE NON-VOLATILE SEMICONDUCTOR MEMORY DRIVE

Arithmetic processing apparatus and method

Method and apparatus for managing software controlled cache of translating the physical memory access of a virtual machine between different levels of translation entities

Loading entries into a TLB in hardware via indirect TLB entries

METHOD, APPARATUS AND SOFTWARE PRODUCT FOR DISTRIBUTED ADDRESS-CHANNEL CALCULATOR FOR MULTI-CHANNEL MEMORY

METHOD, APPARATUS AND SOFTWARE PRODUCT FOR MULTI-CHANNEL MEMORY SANDBOX

Maintaining reverse mappings in a virtualized computer system

Implementing vector memory operations

Buffer management structure with selective flush

Device, system and method of accessing data stored in a memory

Synchronizing a translation lookaside buffer with an extended paging table

Three-tiered translation lookaside buffer hierarchy in a multithreading microprocessor

Generating multiple address space identifiers per virtual machine to switch between protected micro-contexts

Memory management unit directed access to system interfaces

Methods and systems for checking run-time integrity of secure code cross-reference to related applications

Management of persistent memory in a multi-node computer system

Address caching stored translation

Mapping memory segments in a translation lookaside buffer

Maintaining processor resources during architectural events

Storage device reducing a memory management load and computing system using the storage device

Data processing system for logging memory access data

Performing a least recently used (LRU) algorithm for a co-processor

Providing multiple quiesce state machines in a computing environment

System, method and computer program product for providing quiesce filtering for shared memory

Processor, method and computer program product for fast selective invalidation of translation lookaside buffer

System, method and processor for accessing data after a translation lookaside buffer miss

System, method and computer program product for providing a new quiesce state

Serializing translation lookaside buffer access around address translation parameter modification

3-dimensional L2/L3 cache array to hide translation (TLB) delays

Asynchronous memory move across physical nodes with dual-sided communication

Handling of address conflicts during asynchronous memory move operations

Reporting of partially performed memory move

Techniques for multi-level indirect data prefetching

Techniques for prediction-based indirect data prefetching

Memory management unit in a microprocessor system

Maintaining processor resources during architectural events

HANDLING CONCURRENT ADDRESS TRANSLATION CACHE MISSES AND HITS UNDER THOSE MISSES WHILE MAINTAINING COMMAND ORDER

Large-page optimization in virtual memory paging systems

Load page table entry address instruction execution based on an address translation format control field

Dynamic address translation with translation table entry format control for indentifying format of the translation table entry

Dynamic address translation with fetch protection

Dynamic address translation with frame management

Microprocessor architecture having alternative memory access paths

Translation management of logical block addresses and physical block addresses

Method, system, and apparatus for page sizing extension

Using a translation lookaside buffer in a multiple stage memory address translation structure to manage protected microcontexts

Efficient non-transactional write barriers for strong atomicity

Accelerating software lookups by using buffered or ephemeral stores

Providing metadata in a translation lookaside buffer (TLB)

Method and apparatus for performing improved group instructions

Structure for a memory-centric page table walker

Computer system, memory management method and program thereof

Controlling cleaning of data values within a hardware accelerator

Apparatus, system, and method for converting a storage request into an append data storage command

Achieving coherence between dynamically optimized code and original code

Multithreaded processor with lock indicator

PCI express address translation services invalidation synchronization with TCE invalidation

Semiconductor integrated circuit

Iommu with translation request management and methods for managing translation requests

Configurable translation lookaside buffer

Memory module and control method of serial peripheral interface using address cache

Translation lookaside buffer snooping within memory coherent system

Dual mode operating system for a computing device

Adaptive comparison control in a data store

Microprocessor with improved data stream prefetching using multiple transaction look-aside buffers (TLBs)

System and method for generating fast instruction and data interrupts for processor design verification and validation

DEBUGGING SYSTEM, DEBUGGING APPARATUS AND METHOD

Arrangements having security protection

Method and apparatus to trigger synchronization and validation actions upon memory access

METHOD FOR IMPROVING THE PERFORMANCE OF SOFTWARE-MANAGED TLB

Mapping an input data value to a resultant data value

Data processing system

Processing system implementing multiple page size memory organization with multiple translation lookaside buffers having differing characteristics

Processing system implementing variable page size memory organization

Configurable memory system and method for providing atomic counting operations in a memory device

Linear to physical address translation with support for page attributes

System and method for managing addresses in a computing system

Processing of self-modifying code in multi-address-space and multi-processor systems

Arithmetic processor, information processing apparatus and memory access method in arithmetic processor

Method and apparatus for dynamically adjusting page size in a virtual memory range

MULTI-WAFER 3D CAM CELL

Virtual Translation Lookaside Buffer

SEMICONDUCTOR DEVICE HAVING MEMORY ACCESS MECHANISM WITH ADDRESS-TRANSLATING FUNCTION

Latency hiding for a memory management unit page table lookup

Method and Apparatus for Page Table Pre-Fetching in Zero Frame Display Channel

Virtual memory translation with pre-fetch prediction

DATA PROCESSOR

Cache memory

Providing memory consistency in an emulated processing environment

Hybrid dual match line architecture for content addressable memories and other data structures

COHERENT DATA MOVER

Low overhead access to shared on-chip hardware accelerator with memory-based interfaces

Apparatus and method for executing rapid memory management unit emulation and full-system simulator

Efficient on-chip accelerator interfaces to reduce software overhead

Employing a data structure of readily accessible units of memory to facilitate memory access

System and method of improving task switching and page translation performance utilizing a multilevel translation lookaside buffer

Translation data prefetch in an IOMMU

Address translation method and apparatus

Method and apparatus for setting cache policies in a processor

Method and apparatus to search for errors in a translation look-aside buffer

Systems and methods for utilizing an extended translation look-aside buffer having a hybrid memory structure

Flash memory module, storage apparatus using flash memory module as recording medium, and address translation table verification method for flash memory module

Architecture support of memory access coloring

Cache circuitry, data processing apparatus and method for handling write access requests

User-level privilege management

System for generating effective address

Means to share translation lookaside buffer (TLB) entries between different contexts

PREFETCH MECHANISM BASED ON PAGE TABLE ATTRIBUTES

Scalability of virtual TLBs for multi-processor virtual machines

Method and apparatus for faster execution path

Multi-hit detection in associative memories

Transparent multi-hit correction in associative memories

Efficient flushing of translation lookaside buffers in a multiprocessor environment

Circuit having relaxed setup time via reciprocal clock and data gating

Operational efficiency of virtual TLBs

Prefetching in a virtual memory system based upon repeated accesses across page boundaries

Prefetching in a virtual memory system based upon repeated accesses across page boundaries

Method and apparatus for managing the power consumption of a data processing system

Page replacement policy for systems having multiple page sizes

Page replacement policy for systems having multiple page sizes

Filtering and remapping interrupts

Operating system protection against side-channel attacks on secrecy

Method to optimize effective page number to real page number translation path from page table entries match resumption of execution stream

INFORMATION PROCESSING APPARATUS AND INFORMATION PROCESSING METHOD

In-use bits for efficient instruction fetch operations

Method and system for combining page buffer list entries to optimize caching of translated addresses

Synchronizing a translation lookaside buffer to an extended paging table

DEDICATED MECHANISM FOR PAGE MAPPING IN A GPU

Content-addressable memory that supports a priority ordering between banks of differing sizes

Method and system to indicate an exception-triggering page within a microprocessor

CONTROL PROTOCOL AND SIGNALING IN A NEW MEMORY ARCHITECTURE

Network performance in virtualized environments

Miss-under-miss processing and cache flushing

Relocating page tables

Dynamic selection of memory virtualization techniques

Handling concurrent address translation cache misses and hits under those misses while maintaining command order

Memory Management System

Methods and apparatus for providing simultaneous software/hardware cache fill

Hardware Assisted Exception for Software Miss Handling of an I/O Address Translation Cache Miss

Processor and method for altering address translation

Processor comprising an instruction set and registers for simplified opcode access

Data processor and IP module for data processor

Selective address translation for a resource such as a hardware device

Non-intrusive address mapping having a modified address space identifier and circuitry therefor

Data processing system having address translation bypass and method therefor

Clearing selected storage translation buffer entries based on table origin address

Multiprocessor system that supports both coherent and non-coherent memory accesses

Method and apparatus for allowing uninterrupted address translations while performing address translation cache invalidates and other cache operations

Method for command list ordering after multiple cache misses

Method for cache hit under miss collision handling

Method for completing IO commands after an IO translation miss

Translation lookaside buffer manipulation

Data compression method for supporting virtual memory management in a demand paging system

Unbounded transactional memory systems

Arrangements having security protection

Methods and apparatus for handling a cache miss

Address translation table synchronization

Memory access techniques providing for override of page table attributes

Storage device, computer system, and storage device access method

High speed CAM lookup using stored encoded key

Preloading translation buffers

Method and apparatus to perform memory management

Microprocessor with improved data stream prefetching

Microprocessor with improved data stream prefetching

Implementing vector memory operations

Updating multiple levels of translation lookaside buffers (TLBs) field

System and method for accessing non processor-addressable memory

Mitigating context switch cache miss penalty

Method and an apparatus to prevent over subscription and thrashing of translation lookaside buffer (TLB) entries in I/O virtualization hardware

Method and an apparatus to track address translation in I/O virtualization

Multithreaded processor having a source processor core to subsequently delay continued processing of demap operation until responses are received from each of remaining processor cores

Hardware demapping of TLBs shared by multiple threads

Microprocessor with improved data stream prefetching

System and method for synchronizing translation lookaside buffer access in a multithread processor

TLB lock indicator

Microprocessor with improved data stream prefetching

Microprocessor with improved data stream prefetching

Microprocessor with improved data stream prefetching

Semiconductor integrated circuit

Avoiding silent data corruption and data leakage in a virtual environment with multiple guests

Controlling an I/O MMU

Ensuring deadlock free operation for peer to peer traffic in an input/output memory management unit (IOMMU)

Method and apparatus for debugging program code

Fast data breakpoint emulation

Translation lookaside buffer prediction mechanism

Using writeable page tables for memory address translation in a hypervisor environment

Systems and methods for increasing yield of devices having cache memories by inhibiting use of defective cache entries

Preventing multiple translation lookaside buffer accesses for a same page in memory

Memory management in a multiprocessor system

Shared translation look-aside buffer and method

Statement regarding federally sponsored-research or development

Memory attribute speculation

Accessing copy information of MMIO register by guest OS in both active and inactive state of a designated logical processor corresponding to the guest OS

Microprocessor including a configurable translation lookaside buffer

Page replacement policy for systems having multiple page sizes

Method and system for efficient cache locking mechanism

Scalable DMA remapping on a computer bus

Memory management circuitry translation information retrieval during debugging

Prefetch mechanism based on page table attributes

System and method of large page handling in a virtual memory system

System and method for reducing the number of translation buffer invalidates an operating system needs to issue

System and method of improving task switching and page translation performance utilizing a multilevel translation lookaside buffer

Locking entries into translation lookaside buffers

Method and system for optimizing translation lookaside buffer entries

Method and system for a second level address translation in a virtual machine environment

Three-tiered translation lookaside buffer hierarchy in a multithreading microprocessor

Method and apparatus for selecting operating characteristics of a content addressable memory by using a compare mask

System and method for generating effective address

Method to optimize effective page number to real page number translation path from page table entries match resumption of execution stream

System and method to improve hardware pre-fetching using translation hints

Method for updating entries of address conversion buffers in a multi-processor computer system

Methods and apparatus for updating a memory address remapping table

Lazy flushing of translation lookaside buffers

Method and apparatus for utilizing an exception handler to avoid hanging up a CPU when a peripheral device does not respond

Method and apparatus for protecting TLB's VPN from soft errors

Translation lookaside buffer (TLB) suppression for intra-page program counter relative or absolute address branch instructions

Systems and methods for replicating virtual memory on a host computer and debugging using replicated memory