190279 ⎘
Accessing, addressing or allocating within memory systems or architectures; Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems; Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
Memory allocation in a system using memory striping
#1202Apparatus and method for insertion and deletion in multi-dimensional to linear address space translation
#1203Apparatus and method for referencing dense and sparse information in multi-dimensional to linear address space translation
#1204Mechanism for facilitating dynamic and efficient management of translation buffer prefetching in software programs at computing systems
#1205Stride-based translation lookaside buffer (TLB) prefetching with adaptive offset
#1206Migration directives in a unified virtual memory system architecture
#1207Apparatus and method for cloning and snapshotting in multi-dimensional to linear address space translation
#1208Apparatus and method for translation from multi-dimensional to linear address space in storage
#1209Memory system
#1210Translation lookaside buffer entry systems and methods
#1211Vertically integrated storage
#1212Providing snoop filtering associated with a data buffer
#1213Memory address management system and method
#1214Latency reduction for direct memory access operations involving address translation
#1215Apparatus and method for using fields in N-space translation of storage requests
#1216System-on-chip and method of operating the same
#1217Method and apparatus for preventing unauthorized access to contents of a register under certain conditions when performing a hardware table walk (HWTW)
#1218Methods and systems for reducing the amount of time and computing resources that are required to perform a hardware table walk (HWTW)
#1219System and method for providing a command buffer in a memory system
#1220One-cacheable multi-core architecture
#1221Hot memory block table in a solid state storage device
#1222Managing the translation look-aside buffer (TLB) of an emulated machine
#1223System and method for providing an address cache for memory map learning
#1224Storing a system-absolute address (SAA) in a first level translation look-aside buffer (TLB)
#1225Fractal layout of data blocks across multiple devices
#1226Virtual memory management system with reduced latency
#1227Systems and methods for accessing memory
#1228Providing hardware support for shared virtual memory between local and remote physical memory
#1229Page miss handler including wear leveling logic
#1230Overlap checking for a translation lookaside buffer (TLB)
#1231Indexed page address translation to reduce memory footprint in virtualized environments
#1232System and method for out-of-order prefetch instructions in an in-order pipeline
#1233Anticipatorily loading a page of memory
#1234System on chip including memory management unit and memory address translation method thereof
#1235Apparatus and method for tracking TLB flushes on a per thread basis
#1236Apparatus and method for page walk extension for enhanced security checks
#1237Access type protection of memory reserved for use by processor logic
#1238Snoop filter having centralized translation circuitry and shadow tag array
#1239IMAGE FORMING APPARATUS AND METHOD OF TRANSLATING VIRTUAL MEMORY ADDRESS INTO PHYSICAL MEMORY ADDRESS
#1240Dynamic address translation with translation table entry format control for identifying format of the translation table entry
#1241Virtual address based memory reordering
#1242REPORTING ACCESS AND DIRTY PAGES
#1243Processing device with address translation probing and methods
#1244Speculative addressing using a virtual address-to-physical address page crossing buffer
#1245Die-stacked memory device providing data translation
#1246Write endurance management techniques in the logic layer of a stacked memory
#1247Method and system for efficient memory region deallocation
#1248Filtering requests for a translation lookaside buffer
#1249Technique for accessing content-addressable memory
#1250Controlling access to groups of memory pages in a virtualized environment
#1251Translation management instructions for updating address translation data structures in remote processing nodes
#1252Translation management instructions for updating address translation data structures in remote processing nodes
#1253OVERRIDE SYSTEM AND METHOD FOR MEMORY ACCESS MANAGEMENT
#1254Virtual address cache memory, processor and multiprocessor
#1255Flexible page sizes for virtual memory
#1256Multi-stage translation of prefetch requests
#1257Shared virtual memory between a host and discrete graphics device in a computing system
#1258Caching of virtual to physical address translations
#1259Prefetching across page boundaries in hierarchically cached processors
#1260Method and apparatus to shutdown a memory channel
#1261Prefetching based upon return addresses
#1262Store operation with conditional push of a tag value to a queue
#1263Suppressing virtual address translation utilizing bits and instruction tagging
#1264Suppressing virtual address translation utilizing bits and instruction tagging
#1265Configurable I/O address translation data structure
#1266Configurable I/O address translation data structure
#1267Speculative tablewalk promotion
#1268Reducing microprocessor performance loss due to translation table coherency in a multi-processor system
#1269Reducing microprocessor performance loss due to translation table coherency in a multi-processor system
#1270Operational efficiency of virtual TLBs
#1271Efficient memory virtualization in multi-threaded processing units
#1272Detection of conflicts between transactions and page shootdowns
#1273Remapping memory cells based on future endurance measurements
#1274Cache management based on physical memory device characteristics
#1275Cache management based on physical memory device characteristics
#1276PREFETCHING TABLEWALK ADDRESS TRANSLATIONS
#1277MEMORY PROTECTION UNIT IN A VIRTUAL PROCESSING ENVIRONMENT
#1278Asymmetric co-existent address translation structure formats
#1279SELECTABLE ADDRESS TRANSLATION MECHANISMS
#1280Adjunct component to provide full virtualization using paravirtualized hypervisors
#1281REDUCING COLD TLB MISSES IN A HETEROGENEOUS COMPUTING SYSTEM
#1282Selectable address translation mechanisms
#1283System supporting multiple partitions with differing translation formats
#1284System supporting multiple partitions with differing translation formats
#1285Adjunct component to provide full virtualization using paravirtualized hypervisors
#1286Asymmetric co-existent address translation structure formats
#1287Techniques for utilizing translation lookaside buffer entry numbers to improve processor performance
#1288Power savings via dynamic page type selection
#1289Enabling virtualization of a processor resource
#1290Power savings via dynamic page type selection
#1291PROVIDING USAGE STATISTICS FOR VIRTUAL STORAGE
#1292Detection of conflicts between transactions and page shootdowns
#1293Efficient metadata protection system for data storage
#1294Concurrent page table walker control for TLB miss handling
#1295Texel data structure for graphics processing unit programmable shader and method of operation thereof
#1296CONFIGURABLE TRANSLATION LOOKASIDE BUFFER
#1297Oldest operation translation look-aside buffer
#1298Load page table entry address instruction execution based on an address translation format control field
#1299Synchronizing a translation lookaside buffer with an extended paging table
#1300STLB prefetching for a multi-dimension engine
#1301DMA engine with STLB prefetch capabilities and tethered prefetching
#1302System translation look-aside buffer with request-based allocation and prefetching
#1303System translation look-aside buffer integrated in an interconnect
#1304Using a shared last-level TLB to reduce address-translation latency
#1305Methods, systems and devices for hybrid memory management
#1306TLB-walk controlled abort policy for hardware transactional memory
#1307Using broadcast-based TLB sharing to reduce address-translation latency in a shared-memory system with electrical interconnect
#1308All invalidate approach for memory management units
#1309Memory management for a hierarchical memory system
#1310Operating on translation look-aside buffers in a multiprocessor environment
#1311Control flow management for execution of dynamically translated non-native code in a virtual hosting environment
#1312SYSTEMS AND METHODS FOR PROCESSING INSTRUCTIONS WHEN UTILIZING AN EXTENDED TRANSLATION LOOK-ASIDE BUFFER HAVING A HYBRID MEMORY STRUCTURE
#1313MEMORY MANAGEMENT IN A VIRTUALIZATION ENVIRONMENT
#1314Identification and consolidation of page table entries
#1315Page table entry consolidation
#1316Local clearing control
#1317Compare and Replace DAT Table Entry
#1318Translation look-aside table management
#1319Radix table translation of memory
#1320Identification and consolidation of page table entries
#1321Radix table translation of memory
#1322Page table entry consolidation
#1323Address range priority mechanism
#1324PROVIDING USAGE STATISTICS FOR VIRTUAL STORAGE
#1325Caching Frequently Used Addresses of a Page Table Walk
#1326Apparatus and method for accelerating operations in a processor which uses shared virtual memory
#1327Efficient locking of memory pages
#1328Data processing apparatus having cache and translation lookaside buffer
#1329Program execution device and compiler system
#1330Method, apparatus, and system for efficiently handling multiple virtual address mappings during transactional execution canceling the transactional execution upon conflict between physical addresses of transactional accesses within the transactional execution
#1331Address space management while switching optically-connected memory
#1332Memory switching protocol when switching optically-connected memory
#1333Remote memory management when switching optically-connected memory
#1334Address space management while switching optically-connected memory
#1335Switching optically connected memory
#1336Hybrid address translation
#1337Translation lookaside buffer for multiple context compute engine
#1338Hybrid address translation
#1339Virtualization system using hardware assistance for shadow page table coherence
#1340Delayed replacement of TLB entries
#1341Shared virtual memory between a host and discrete graphics device in a computing system
#1342Multiple page size memory management unit
#1343Systems and methods for accessing a unified translation lookaside buffer
#1344Maintaining processor resources during architectural evens
#1345System and method for supporting finer-grained copy-on-write page sizes
#1346Memory address translation
#1347Memory management unit with prefetch ability
#1348Data processing system operable in single and multi-thread modes and having multiple caches and method of operation
#1349Techniques for storing data and tags in different memory arrays
#1350Maintaining processor resources during architectural events
#1351Invalidating translation lookaside buffer entries in a virtual machine system
#1352OBJECT-BASED MEMORY STORAGE
#1353Memory address translation-based data encryption with integrated encryption engine
#1354Information processing device including host device and semiconductor memory device having plurality of address conversion information
#1355Method and apparatus for accessing physical memory from a CPU or processing element in a high performance manner
#1356Direct memory address for solid-state drives
#1357Non-volatile memory devices using a mapping manager
#1358Non-Allocating Memory Access with Physical Address
#1359Streaming translation in display pipe
#1360I/O controller and method for operating an I/O controller
#1361Sub page and page memory management apparatus and method
#1362Handling Virtual-to-Physical Address Translation Failures
#1363Method, system, and apparatus for page sizing extension
#1364Software translation lookaside buffer for persistent pointer management
#1365Methods and apparatus to access memory using runtime characteristics
#1366Integrated circuit including pulse control logic having shared gating control
#1367Address translation checking device, central processing unit, and address translation checking method
#1368Memory management unit speculative hardware table walk scheme
#1369Method and system for providing hardware support for memory protection and virtual memory address translation for a virtual machine
#1370Maintaining processor resources during architectural events
#1371Direct memory address for solid-state drives
#1372Address translation device, processing device and control method of processing device
#1373ADDRESS TRANSLATION UNIT, METHOD OF CONTROLLING ADDRESS TRANSLATION UNIT AND PROCESSOR
#1374METHODS AND APPARATUS FOR FAST CONTEXT SWITCHING IN A VIRTUALIZED SYSTEM
#1375Synchronizing a translation lookaside buffer with an extended paging table
#1376Mechanisms to accelerate transactions using buffered stores
#1377Memory management unit tag memory
#1378Memory management unit TAG memory with CAM evaluate signal
#1379Mechanisms to accelerate transactions using buffered stores
#1380Mechanisms to accelerate transactions using buffered stores
#1381PREVENTION OF RACE CONDITIONS IN LIBRARY CODE THROUGH MEMORY PAGE-FAULT HANDLING MECHANISMS
#1382Generating multiple address space identifiers per virtual machine to switch between protected micro-contexts
#1383Memory signal buffers and modules supporting variable access granularity
#1384Implementing vector memory operations
#1385Method and apparatus for TLB shoot-down in a heterogeneous computing system supporting shared virtual memory
#1386Multi-core shared page miss handler
#1387Dynamic storage tiering
#1388Optimizing TLB entries for mixed page size storage in contiguous memory
#1389Dynamic sizing of translation lookaside buffer for power reduction
#1390Method and apparatus for managing software controlled cache of translating the physical memory access of a virtual machine between different levels of translation entities
#1391Dynamic pinning of virtual pages shared between different type processors of a heterogeneous computing platform
#1392Apparatus and Method for Accelerated Hardware Page Table Walk
#1393Performing memory accesses while omitting unnecessary address translations
#1394Systems and methods for utilizing an extended translation look-aside buffer having a hybrid memory structure
#1395Relocating page tables and data amongst memory modules in a virtualized environment
#1396Providing metadata in a translation lookaside buffer (TLB)
#1397Facilitating data coherency using in-memory tag bits and tag test instructions
#1398MEMORY MANAGEMENT UNIT, APPARATUSES INCLUDING THE SAME, AND METHOD OF OPERATING THE SAME
#1399Facilitating data coherency using in-memory tag bits and tag test instructions
#1400Memory system and operating method thereof
#1401Control of on-die system fabric blocks
#1402Virtual address mapping using rule based aliasing to achieve fine grained page translation
#1403Methods and apparatus for handling a cache miss
#1404Large-page optimization in virtual memory paging systems
#1405Seamless interface for multi-threaded core accelerators
#1406Implementing TLB Synchronization for Systems with Shared Virtual Memory Between Processing Devices
#1407Protecting large objects within an advanced synchronization facility
#1408Memory management unit with pre-filling capability
#1409Logical address translation
#1410Cache for storing multiple forms of information and a method for controlling a cache storing multiple forms of information
#1411Storage Device and Computer Using the Same
#1412Page invalidation processing with setting of storage key to predefined value
#1413Reducing interprocessor communications pursuant to updating of a storage key
#1414Address translation caching and I/O cache performance improvement in virtualized environments
#1415Memory management unit and apparatuses having same
#1416Memory address translation
#1417TRANSLATION LOOK-ASIDE BUFFER INCLUDING HAZARD STATE
#1418Executing a perform frame management instruction
#1419Method and system for caching attribute data for matching attributes with physical addresses
#1420Power filter in data translation look-aside buffer based on an input linear address
#1421Management of persistent memory in a multi-node computer system
#1422Dynamic address translation with translation table entry format control for identifying format of the translation table entry
#1423Memory system comprising translation lookaside buffer and translation information buffer and related method of operation
#1424Semiconductor memory device
#1425Data structure for enforcing consistent per-physical page cacheability attributes
#1426Streaming translation in display pipe
#1427Multi-wafer 3D CAM cell
#1428Translation Lookaside Buffer Structure Including a Data Array Having an Integrated Multiplexer
#1429Translation lookaside buffer structure including an output comparator
#1430Translation Lookaside Buffer Structure Including a Data Array Storing an Address Selection Signal
#1431Translation Lookaside Buffer Structure Including a Data Array Sense Amplifier and Fast Compare Unit
#1432Location of memory management translations in an emulated processor
#1433Integrated circuit including pulse control logic having shared gating control
#1434Invalidating a range of two or more translation table entries and instruction therefore
#1435Methods and apparatus for virtualization in an integrated circuit
#1436Invalidating translation lookaside buffer entries in a virtual machine (VM) system
#1437Synchronizing a translation lookaside buffer with an extended paging table
#1438Remapping of inoperable memory blocks
#1439Translation lookaside buffer (TLB) with reserved areas for specific sources
#1440Dynamic memory affinity reallocation after partition migration
#1441ADDRESS CONVERSION APPARATUS
#1442Apparatus, method, and system for implementing micro page tables
#1443Computer-readable, non-transitory medium storing memory access control program, memory access control method, and information processing apparatus
#1444Translation lookaside buffer
#1445Real address accessing in a coprocessor executing on behalf of an unprivileged process
#1446METHOD AND APPARATUS FOR HANDLING CRITICAL BLOCKING OF STORE-TO-LOAD FORWARDING
#1447Methods and apparatus for burst data transfers between double data rate (DDR) memories and embedded processors during training
#1448Opportunistic improvement of MMIO request handling based on target reporting of space requirements
#1449Image forming apparatus and method of translating virtual memory address into physical memory address
#1450Method and system for providing distributed programming environment using distributed spaces, and computer readable recording medium
#1451Recording dirty information in software distributed shared memory systems
#1452Method and system for providing hardware support for memory protection and virtual memory address translation for a virtual machine
#1453System and method to manage a translation lookaside buffer
#1454Load page table entry address instruction execution based on an address translation format control field
#1455MULTITHREAD PROCESSOR AND DIGITAL TELEVISION SYSTEM
#1456Data processing apparatus for storing address translations
#1457High performance cache translation look-aside buffer (TLB) lookups using multiple page size prediction
#1458Region based technique for accurately predicting memory accesses
#1459Translating translation requests having associated priorities
#1460Page fault prediction for processing vector instructions
#1461Apparatus and method for handling access operations issued to local cache structures within a data processing apparatus
#1462Redundant multithreading processor
#1463Persistent memory for processor main memory
#1464Locking entries into translation lookaside buffers
#1465Configuring surrogate memory accessing agents using non-priviledged processes
#1466Multiple page size segment encoding
#1467Efficient support of multiple page size segments
#1468Accelerating software lookups by using buffered or ephemeral stores
#1469NON-COMMITTING STORE INSTRUCTIONS
#1470Maintaining reverse mappings in a virtualized computer system
#1471Efficient non-transactional write barriers for strong atomicity
#1472Pre-fetching for a sibling cache
#1473Virtual address cache memory, processor and multiprocessor
#1474Methods and apparatus for sum of address compare write recode and compare reduction
#1475Multi-petascale highly efficient parallel supercomputer
#1476Providing metadata in a translation lookaside buffer (TLB)
#1477IOMMU architected TLB support
#1478Optimizing TLB entries for mixed page size storage in contiguous memory
#1479Relocating page tables and data amongst memory modules in a virtualized environment
#1480Secure processor and a program for a secure processor
#1481Memory access control device, integrated circuit, memory access control method, and data processing device
#1482Systems and methods implementing non-shared page tables for sharing memory resources managed by a main operating system with accelerator devices
#1483Software assisted translation lookaside buffer search mechanism
#1484System, method, and apparatus for a cache flush of a range of pages and TLB invalidation of a range of entries
#1485Delayed replacement of cache entries
#1486Apparatuses, Systems, and Methods for Reducing Translation Lookaside Buffer (TLB) Lookups
#1487Mechanisms to accelerate transactions using buffered stores
#1488Page invalidation processing with setting of storage key to predefined value
#1489Reducing interprocessor communications pursuant to updating of a storage key
#1490Flash memory module, storage apparatus using flash memory module as recording medium and address translation table verification method for flash memory module
#1491Preventing duplicate entries in a non-blocking TLB structure that supports multiple page sizes
#1492Maintaining data coherence by using data domains
#1493DRAM control method and the DRAM controller utilizing the same
#1494Maintaining processor resources during architectural events
#1495Dynamically replicated memory
#1496Clearing selected storage translation buffer entries bases on table origin address
#1497Efficiency of hardware memory access using dynamically replicated memory
#1498Address translation unit with multiple virtual queues
#1499Input-output memory management unit (IOMMU) and method for tracking memory pages during virtual-machine migration
#1500Memory management unit